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From: Neil Armstrong <neil.armstrong@linaro.org>
To: Jacky Chou <jacky_chou@aspeedtech.com>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
	"kwilczynski@kernel.org" <kwilczynski@kernel.org>,
	"mani@kernel.org" <mani@kernel.org>,
	"robh@kernel.org" <robh@kernel.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"joel@jms.id.au" <joel@jms.id.au>,
	"andrew@codeconstruct.com.au" <andrew@codeconstruct.com.au>,
	"vkoul@kernel.org" <vkoul@kernel.org>,
	"kishon@kernel.org" <kishon@kernel.org>,
	"linus.walleij@linaro.org" <linus.walleij@linaro.org>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
	"openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>,
	"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>
Cc: "elbadrym@google.com" <elbadrym@google.com>,
	"romlem@google.com" <romlem@google.com>,
	"anhphan@google.com" <anhphan@google.com>,
	"wak@google.com" <wak@google.com>,
	"yuxiaozhang@google.com" <yuxiaozhang@google.com>,
	BMC-SW <BMC-SW@aspeedtech.com>
Subject: Re: 回覆: [PATCH 0/7] Add ASPEED PCIe Root Complex support
Date: Tue, 24 Jun 2025 09:29:11 +0200	[thread overview]
Message-ID: <754d260c-1a31-494e-af06-49f6aae1813f@linaro.org> (raw)
In-Reply-To: <SEYPR06MB513414A5AE38EE6749A2902C9D7CA@SEYPR06MB5134.apcprd06.prod.outlook.com>

On 20/06/2025 10:20, Jacky Chou wrote:
>>> This series has been tested on AST2600/AST2700 platforms and enables
>>> PCIe device enumeration and operation.
>>>
>>> Feedback and review are welcome.
>>
>> So it seems all PCIe RC code is bundled in a single driver and there's no PCIe
>> PHY driver code, is there a reason for that ? If yes I think it should be described
>> in the cover letter.
>>
> 
> Yes, because our design includes the PCIe RC and the PCIe EPs.
> The two functions use the same PCIe PHY and are mutually exclusive.
> And there are different configurations on RC and EP.
> Therefore, we do not use a phy driver to configure our PCIe but use
> the phandle of phy syscon to set the RC and EP drivers separately.

I don't get why a PHY drive could not exist, it could be used by either
the RC or EP PCIe driver in an exclusive way.

Neil

> 
> I will add more description in next version.
> 
> Thanks,
> Jacky
> 


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  reply	other threads:[~2025-06-24  7:45 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-13  3:29 [PATCH 0/7] Add ASPEED PCIe Root Complex support Jacky Chou
2025-06-13  3:29 ` [PATCH 1/7] dt-bindings: phy: Add document for ASPEED PCIe PHY Jacky Chou
2025-06-13  9:14   ` neil.armstrong
2025-06-20  5:03     ` 回覆: " Jacky Chou
2025-06-13  9:44   ` Krzysztof Kozlowski
2025-06-20  8:29     ` 回覆: " Jacky Chou
2025-06-13  3:29 ` [PATCH 2/7] dt-bindings: pci: Add document for ASPEED PCIe Config Jacky Chou
2025-06-13  9:46   ` Krzysztof Kozlowski
2025-06-20  8:32     ` 回覆: " Jacky Chou
2025-06-13 15:58   ` Bjorn Helgaas
2025-06-20  5:27     ` Jacky Chou
2025-06-13  3:29 ` [PATCH 3/7] dt-bindings: pci: Add document for ASPEED PCIe RC Jacky Chou
2025-06-13  9:50   ` Krzysztof Kozlowski
2025-06-20  8:36     ` Jacky Chou
2025-06-25 21:04   ` Rob Herring
2025-06-27  9:59     ` 回覆: " Jacky Chou
2025-06-13  3:29 ` [PATCH 4/7] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST ctrl pin Jacky Chou
2025-06-13  9:51   ` Krzysztof Kozlowski
2025-06-20  8:36     ` Jacky Chou
2025-06-13 15:59   ` Bjorn Helgaas
2025-06-13  3:29 ` [PATCH 5/7] ARM: dts: aspeed-g6: Add PCIe RC node Jacky Chou
2025-06-13 15:54   ` Bjorn Helgaas
2025-06-20  5:24     ` 回覆: " Jacky Chou
2025-06-24 15:28       ` Bjorn Helgaas
2025-06-25  8:27         ` 回覆: " Jacky Chou
2025-06-25 22:16           ` Bjorn Helgaas
2025-06-27 10:02             ` Jacky Chou
2025-06-13  3:30 ` [PATCH 6/7] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-06-18 12:15   ` Linus Walleij
2025-06-20  7:09   ` Andrew Jeffery
2025-06-13  3:30 ` [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver Jacky Chou
2025-06-13  9:54   ` Krzysztof Kozlowski
2025-06-23  2:42     ` 回覆: " Jacky Chou
2025-06-13 12:03   ` Ilpo Järvinen
2025-06-23  5:41     ` Jacky Chou
2025-06-24 10:50       ` Ilpo Järvinen
2025-06-24 11:11         ` 回覆: " Jacky Chou
2025-06-24 15:40       ` Bjorn Helgaas
2025-06-25  8:32         ` 回覆: " Jacky Chou
2025-06-13 16:28   ` Bjorn Helgaas
2025-06-20  6:05     ` 回覆: " Jacky Chou
2025-06-24 15:33       ` Bjorn Helgaas
2025-06-14  2:07   ` kernel test robot
2025-06-19  8:14   ` kernel test robot
2025-06-13  9:18 ` [PATCH 0/7] Add ASPEED PCIe Root Complex support neil.armstrong
2025-06-20  8:20   ` 回覆: " Jacky Chou
2025-06-24  7:29     ` Neil Armstrong [this message]
2025-06-24 10:54       ` 回覆: " Jacky Chou
2025-06-16 21:46 ` Rob Herring (Arm)

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