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charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 6/12/2026 12:54 PM, Dmitry Baryshkov wrote: > On Fri, Jun 12, 2026 at 12:13:04PM +0530, Kathiravan Thirumoorthy wrote: >> On 6/12/2026 11:44 AM, Dmitry Baryshkov wrote: >>> On Fri, Jun 12, 2026 at 08:22:02AM +0530, Kathiravan Thirumoorthy wrote: >>>> On 6/12/2026 1:52 AM, Dmitry Baryshkov wrote: >>>>> On Tue, Jun 09, 2026 at 03:46:56PM +0530, Kathiravan Thirumoorthy wrote: >>>>>> On 6/8/2026 12:26 PM, Dmitry Baryshkov wrote: >>>>>>> On Tue, Jun 02, 2026 at 02:40:18PM +0530, Kathiravan Thirumoorthy wrote: >>>>>>>> The IPQ9650 platform has three Gen3 2-lane PCIe controllers and two Gen3 >>>>>>>> 1-lane PCIe controllers. The PHY instances also require the on-chip refgen >>>>>>>> supply. >>>>>>>> >>>>>>>> Add the IPQ9650 Gen3 x1 and x2 QMP PCIe PHY configurations, including the >>>>>>>> refgen regulator supply. >>>>>>>> >>>>>>>> Signed-off-by: Kathiravan Thirumoorthy >>>>>>>> --- >>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 220 +++++++++++++++++++++++++++++++ >>>>>>>> 1 file changed, 220 insertions(+) >>>>>>>> >>>>>>>> @@ -3378,6 +3524,10 @@ static const char * const qmp_phy_vreg_l[] = { >>>>>>>> "vdda-phy", "vdda-pll", >>>>>>>> }; >>>>>>>> +static const char * const ipq9650_qmp_phy_vreg_l[] = { >>>>>>>> + "refgen", >>>>>>>> +}; >>>>>>> Now vdda-phy / vdda-pll supplies? >>>>>> Cross checked with HW team again. Along with refgen, there is a on-chip LDO >>>>>> which supplies fixed voltage to the PHYs. It is enabled upon system power on >>>>>> and no SW intervention is required. >>>>> What is it being powered by? MX? CX? >>>> It is driven by CX. >>> I assume that there is no CX collapse on IPQ9650? Is CX not scaling on >>> this chip. Please provide some details on the commit message. >> That's right. No CX collapse on IPQ9650. Let me rewrite the commit message >> as below. Hope its okay. >> >> -- >> >> Add support for the IPQ9650 platform, which includes three Gen3 x2 PCIe >> controllers and two Gen3 x1 PCIe controllers. The PHY instances require the >> on-chip refgen supply. >> >> Add the IPQ9650 Gen3 x1 and x2 QMP PCIe PHY configurations along with the >> refgen regulator supply. Note that an on-chip LDO, driven by the SoC CX, >> supplies the PHY voltages without requiring software control. Note that CX >> power collapse is not supported on IPQ9650. > ...neither CX power collapse nor rail scaling... > > LGTM. Thanks much. Have sent V2. Please have a look. > > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy