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Wed, 28 Aug 2024 09:41:43 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47S9fgGA014181 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Aug 2024 09:41:42 GMT Received: from [10.239.29.179] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 28 Aug 2024 02:41:36 -0700 Message-ID: <79a294b3-90a7-4900-bac1-281d321c9a55@quicinc.com> Date: Wed, 28 Aug 2024 17:41:32 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/8] phy: qcom-qmp: pcs-pcie: Add v6.30 register offsets To: Krzysztof Kozlowski CC: , , , , , , , , , , , , , , , , , , , , , , References: <20240827063631.3932971-1-quic_qianyu@quicinc.com> <20240827063631.3932971-2-quic_qianyu@quicinc.com> <2ojutgxk4kplxwrxxcq5zorejuohbow7dr6lhl4cwndkwzvxf6@lxg4um6krdnh> Content-Language: en-US From: Qiang Yu In-Reply-To: <2ojutgxk4kplxwrxxcq5zorejuohbow7dr6lhl4cwndkwzvxf6@lxg4um6krdnh> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: qcWtSUmrOLNrIVb0U78pxP9xNMLSlD5q X-Proofpoint-GUID: qcWtSUmrOLNrIVb0U78pxP9xNMLSlD5q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-28_03,2024-08-27_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 clxscore=1011 priorityscore=1501 lowpriorityscore=0 spamscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408280069 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240828_024151_767210_38E2A5A5 X-CRM114-Status: GOOD ( 14.59 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 8/27/2024 7:37 PM, Krzysztof Kozlowski wrote: > On Mon, Aug 26, 2024 at 11:36:24PM -0700, Qiang Yu wrote: >> x1e80100 SoC uses QMP phy with version v6.30 for PCIe Gen4 x8. Add the new >> PCS PCIE specific offsets in a dedicated header file. >> >> Signed-off-by: Qiang Yu >> --- >> .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 +++++++++++++++++++ >> 1 file changed, 25 insertions(+) >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h >> new file mode 100644 >> index 000000000000..5a58ff197e6e >> --- /dev/null >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h >> @@ -0,0 +1,25 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved. >> + */ >> + >> +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_30_H_ >> +#define QCOM_PHY_QMP_PCS_PCIE_V6_30_H_ >> + >> +/* Only for QMP V6_30 PHY - PCIE have different offsets than V6 */ >> +#define QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2 0x014 >> +#define QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG 0x020 >> +#define QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE 0x024 >> +#define QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS 0x098 >> +#define QPHY_PCIE_V6_30_PCS_EQ_CONFIG1 0x0a8 >> +#define QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME 0x0f8 >> +#define QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME 0x0fc >> +#define QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5 0x110 >> +#define QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN 0x164 >> +#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1 0x184 >> +#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3 0x18c >> +#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5 0x194 >> +#define QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5 0x1b4 >> +#define QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5 0x1c8 > There is no user of these. Squash it with the user, because there is > little point in adding dead code. > > Best regards, > Krzysztof OK, will squash this three patches related to phy setting into one patch. Thanks, Qiang -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy