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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-53d5399014dsm2475887173.59.2025.09.19.13.14.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Sep 2025 13:14:07 -0700 (PDT) Message-ID: <804ea57f-699f-41cc-a27c-844f107e627f@riscstar.com> Date: Fri, 19 Sep 2025 15:14:05 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/6] dt-bindings: phy: spacemit: introduce PCIe root complex To: Manivannan Sadhasivam Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, vkoul@kernel.org, kishon@kernel.org, dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, tglx@linutronix.de, johan+linaro@kernel.org, thippeswamy.havalige@amd.com, namcao@linutronix.de, mayank.rana@oss.qualcomm.com, shradha.t@samsung.com, inochiama@gmail.com, quic_schintav@quicinc.com, fan.ni@samsung.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250813184701.2444372-1-elder@riscstar.com> <20250813184701.2444372-4-elder@riscstar.com> Content-Language: en-US From: Alex Elder In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250919_131409_314842_87AC2B52 X-CRM114-Status: GOOD ( 25.38 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 9/15/25 3:14 AM, Manivannan Sadhasivam wrote: > On Wed, Aug 13, 2025 at 01:46:57PM GMT, Alex Elder wrote: > > Subject should have 'pci' prefix, not 'phy'. OK I'll update that in the next version. >> Add the Device Tree binding for the PCIe root complex found on the >> SpacemiT K1 SoC. This device is derived from the Synopsys Designware >> PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2 >> link speeds (5 GT/sec). One of the ports uses a combo PHY, which is >> typically used to support a USB 3 port. >> >> Signed-off-by: Alex Elder >> --- >> .../bindings/pci/spacemit,k1-pcie-rc.yaml | 141 ++++++++++++++++++ >> 1 file changed, 141 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml >> new file mode 100644 >> index 0000000000000..6bcca2f91a6fd >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml >> @@ -0,0 +1,141 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-rc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: SpacemiT K1 PCI Express Root Complex >> + >> +maintainers: >> + - Alex Elder >> + >> +description: >> + The SpacemiT K1 SoC PCIe root complex controller is based on the >> + Synopsys DesignWare PCIe IP. >> + >> +properties: >> + compatible: >> + const: spacemit,k1-pcie-rc.yaml >> + >> + reg: >> + items: >> + - description: DesignWare PCIe registers >> + - description: ATU address space >> + - description: PCIe configuration space >> + - description: Link control registers >> + >> + reg-names: >> + items: >> + - const: dbi >> + - const: atu >> + - const: config >> + - const: link >> + >> + clocks: >> + items: >> + - description: DWC PCIe Data Bus Interface (DBI) clock >> + - description: DWC PCIe application AXI-bus Master interface clock >> + - description: DWC PCIe application AXI-bus Slave interface clock. >> + >> + clock-names: >> + items: >> + - const: dbi >> + - const: mstr >> + - const: slv >> + >> + resets: >> + items: >> + - description: DWC PCIe Data Bus Interface (DBI) reset >> + - description: DWC PCIe application AXI-bus Master interface reset >> + - description: DWC PCIe application AXI-bus Slave interface reset. >> + - description: Global reset; must be deasserted for PHY to function >> + >> + reset-names: >> + items: >> + - const: dbi >> + - const: mstr >> + - const: slv >> + - const: global >> + >> + interrupts-extended: >> + maxItems: 1 > > What is the purpose of this property? Is it for MSI or INTx? It is for MSIs, which are translated into this interrupt. I'll add a short description indicating this. Is there a better way to represent this? >> + >> + spacemit,syscon-pmu: >> + description: >> + PHandle that refers to the APMU system controller, whose >> + regmap is used in managing resets and link state. >> + $ref: /schemas/types.yaml#/definitions/phandle >> + >> + device_type: >> + const: pci >> + >> + max-link-speed: >> + const: 2 > > Why do you need to limit it to 5 GT/s always? It's what the hardware overview says is the speed of the ports. PCIE PortA Gen2x1 PCIE PortB Gen2x2 PCIE PortC Gen2x2 But I think what you're asking might be "why do you need to specify in DT that the link speed is limited". And in that case, I realize now that it is not needed. I will specify dw_pcie->max_link_speed to 2 before calling dw_pcie_host_init(). If that's not what you meant, please let me know. >> + num-viewport: >> + const: 8 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - resets >> + - reset-names >> + - spacemit,syscon-pmu >> + - "#address-cells" >> + - "#size-cells" >> + - device_type >> + - max-link-speed > > Same comment as above. > >> + - bus-range >> + - num-viewport >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + pcie0: pcie@ca000000 { >> + compatible = "spacemit,k1-pcie-rc"; >> + reg = <0x0 0xca000000 0x0 0x00001000>, >> + <0x0 0xca300000 0x0 0x0001ff24>, >> + <0x0 0x8f000000 0x0 0x00002000>, >> + <0x0 0xc0b20000 0x0 0x00001000>; >> + reg-names = "dbi", >> + "atu", >> + "config", >> + "link"; >> + >> + ranges = <0x01000000 0x8f002000 0x0 0x8f002000 0x0 0x100000>, > > I/O port CPU address starts from 0. First, I'm not sure what this comment means. But second, this ranges value (which I'm sure I just copied from the working DTS file) somehow got munged. I know there were other errors in this YAML file that I have to fix, and I'll fix this too. Thank you Mani. -Alex > > - Mani > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy