* [PATCH] dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema
@ 2025-06-07 21:26 Rob Herring (Arm)
2025-06-09 8:01 ` Miquel Raynal
0 siblings, 1 reply; 2+ messages in thread
From: Rob Herring (Arm) @ 2025-06-07 21:26 UTC (permalink / raw)
To: Miquel Raynal, Vinod Koul, Kishon Vijay Abraham I,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-phy, devicetree, linux-kernel
Convert the Marvell CP110 combo PHY binding to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/phy/marvell,comphy-cp110.yaml | 154 ++++++++++++++++++
.../bindings/phy/phy-mvebu-comphy.txt | 94 -----------
MAINTAINERS | 2 +-
3 files changed, 155 insertions(+), 95 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
diff --git a/Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml b/Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
new file mode 100644
index 000000000000..d9501df42886
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/marvell,comphy-cp110.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MVEBU COMPHY Controller
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+
+description: >
+ COMPHY controllers can be found on the following Marvell MVEBU SoCs:
+
+ * Armada 7k/8k (on the CP110)
+ * Armada 3700
+
+ It provides a number of shared PHYs used by various interfaces (network, SATA,
+ USB, PCIe...).
+
+properties:
+ compatible:
+ enum:
+ - marvell,comphy-cp110
+ - marvell,comphy-a3700
+
+ reg:
+ minItems: 1
+ items:
+ - description: Generic COMPHY registers
+ - description: Lane 1 (PCIe/GbE) registers (Armada 3700)
+ - description: Lane 0 (USB3/GbE) registers (Armada 3700)
+ - description: Lane 2 (SATA/USB3) registers (Armada 3700)
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: comphy
+ - const: lane1_pcie_gbe
+ - const: lane0_usb3_gbe
+ - const: lane2_sata_usb3
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ clocks:
+ maxItems: 3
+ description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
+
+ clock-names:
+ items:
+ - const: mg_clk
+ - const: mg_core_clk
+ - const: axi_clk
+
+ marvell,system-controller:
+ description: Phandle to the Marvell system controller (CP110 only)
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+patternProperties:
+ '^phy@[0-2]$':
+ description: A COMPHY lane child node
+ type: object
+ additionalProperties: false
+
+ properties:
+ reg:
+ description: COMPHY lane number
+
+ '#phy-cells':
+ const: 1
+
+ required:
+ - reg
+ - '#phy-cells'
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: marvell,comphy-a3700
+
+ then:
+ properties:
+ clocks: false
+ clock-names: false
+
+ required:
+ - reg-names
+
+ else:
+ required:
+ - marvell,system-controller
+
+examples:
+ - |
+ phy@120000 {
+ compatible = "marvell,comphy-cp110";
+ reg = <0x120000 0x6000>;
+ clocks = <&clk 1 5>, <&clk 1 6>, <&clk 1 18>;
+ clock-names = "mg_clk", "mg_core_clk", "axi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ marvell,system-controller = <&syscon0>;
+
+ phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+ };
+
+ - |
+ phy@18300 {
+ compatible = "marvell,comphy-a3700";
+ reg = <0x18300 0x300>,
+ <0x1F000 0x400>,
+ <0x5C000 0x400>,
+ <0xe0178 0x8>;
+ reg-names = "comphy",
+ "lane1_pcie_gbe",
+ "lane0_usb3_gbe",
+ "lane2_sata_usb3";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ comphy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ comphy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ comphy2: phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
deleted file mode 100644
index 5ffd0f55d010..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-MVEBU comphy drivers
---------------------
-
-COMPHY controllers can be found on the following Marvell MVEBU SoCs:
-* Armada 7k/8k (on the CP110)
-* Armada 3700
-It provides a number of shared PHYs used by various interfaces (network, SATA,
-USB, PCIe...).
-
-Required properties:
-
-- compatible: should be one of:
- * "marvell,comphy-cp110" for Armada 7k/8k
- * "marvell,comphy-a3700" for Armada 3700
-- reg: should contain the COMPHY register(s) location(s) and length(s).
- * 1 entry for Armada 7k/8k
- * 4 entries for Armada 3700 along with the corresponding reg-names
- properties, memory areas are:
- * Generic COMPHY registers
- * Lane 1 (PCIe/GbE)
- * Lane 0 (USB3/GbE)
- * Lane 2 (SATA/USB3)
-- marvell,system-controller: should contain a phandle to the system
- controller node (only for Armada 7k/8k)
-- #address-cells: should be 1.
-- #size-cells: should be 0.
-
-Optional properlties:
-
-- clocks: pointers to the reference clocks for this device (CP110 only),
- consequently: MG clock, MG Core clock, AXI clock.
-- clock-names: names of used clocks for CP110 only, must be :
- "mg_clk", "mg_core_clk" and "axi_clk".
-
-A sub-node is required for each comphy lane provided by the comphy.
-
-Required properties (child nodes):
-
-- reg: COMPHY lane number.
-- #phy-cells : from the generic PHY bindings, must be 1. Defines the
- input port to use for a given comphy lane.
-
-Examples:
-
- CP11X_LABEL(comphy): phy@120000 {
- compatible = "marvell,comphy-cp110";
- reg = <0x120000 0x6000>;
- marvell,system-controller = <&CP11X_LABEL(syscon0)>;
- clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
- <&CP11X_LABEL(clk) 1 18>;
- clock-names = "mg_clk", "mg_core_clk", "axi_clk";
- #address-cells = <1>;
- #size-cells = <0>;
-
- CP11X_LABEL(comphy0): phy@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
-
- CP11X_LABEL(comphy1): phy@1 {
- reg = <1>;
- #phy-cells = <1>;
- };
- };
-
- comphy: phy@18300 {
- compatible = "marvell,comphy-a3700";
- reg = <0x18300 0x300>,
- <0x1F000 0x400>,
- <0x5C000 0x400>,
- <0xe0178 0x8>;
- reg-names = "comphy",
- "lane1_pcie_gbe",
- "lane0_usb3_gbe",
- "lane2_sata_usb3";
- #address-cells = <1>;
- #size-cells = <0>;
-
-
- comphy0: phy@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
-
- comphy1: phy@1 {
- reg = <1>;
- #phy-cells = <1>;
- };
-
- comphy2: phy@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
- };
diff --git a/MAINTAINERS b/MAINTAINERS
index 5defb941c141..8fc2f21de224 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14495,7 +14495,7 @@ MARVELL ARMADA 3700 PHY DRIVERS
M: Miquel Raynal <miquel.raynal@bootlin.com>
S: Maintained
F: Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
-F: Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
+F: Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
F: drivers/phy/marvell/phy-mvebu-a3700-comphy.c
F: drivers/phy/marvell/phy-mvebu-a3700-utmi.c
--
2.47.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema
2025-06-07 21:26 [PATCH] dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema Rob Herring (Arm)
@ 2025-06-09 8:01 ` Miquel Raynal
0 siblings, 0 replies; 2+ messages in thread
From: Miquel Raynal @ 2025-06-09 8:01 UTC (permalink / raw)
To: Rob Herring (Arm)
Cc: Vinod Koul, Kishon Vijay Abraham I, Krzysztof Kozlowski,
Conor Dooley, linux-phy, devicetree, linux-kernel
Hi Rob,
Thanks for the conversion.
On 07/06/2025 at 16:26:03 -05, "Rob Herring (Arm)" <robh@kernel.org> wrote:
> Convert the Marvell CP110 combo PHY binding to DT schema format. It's a
> straight forward conversion.
>
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
[...]
> +properties:
> + compatible:
> + enum:
> + - marvell,comphy-cp110
> + - marvell,comphy-a3700
> +
> + reg:
> + minItems: 1
> + items:
> + - description: Generic COMPHY registers
Would you mind to add "(Armada 7k/8k)" here? This information was in the
description and got lost. Armada 7k/8k had (IIRC) a number of
Application Processors and Co-Processors, it might not be
straightforward to guess what "cp110" means to people not familiar with
Marvell naming otherwise?
> + - description: Lane 1 (PCIe/GbE) registers (Armada 3700)
> + - description: Lane 0 (USB3/GbE) registers (Armada 3700)
> + - description: Lane 2 (SATA/USB3) registers (Armada 3700)
> +
> + reg-names:
> + minItems: 1
minItems should probably be 4 as it is only required (and mandatory) for
the marvell,comphy-a3700 compatible? I do not think we intended to ask
for a reg-names property when there was just one entry (see
armada-cp11x.dtsi).
> + items:
> + - const: comphy
> + - const: lane1_pcie_gbe
> + - const: lane0_usb3_gbe
> + - const: lane2_sata_usb3
> +
> + '#address-cells':
> + const: 1
Should be required?
> +
> + '#size-cells':
> + const: 0
Should be required as well?
> +
> + clocks:
> + maxItems: 3
> + description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
> +
> + clock-names:
> + items:
> + - const: mg_clk
> + - const: mg_core_clk
> + - const: axi_clk
> +
> + marvell,system-controller:
> + description: Phandle to the Marvell system controller (CP110 only)
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> +patternProperties:
> + '^phy@[0-2]$':
Technically, these nodes are also mandatory, I don't remember if we can
mark them as such in the "required" section though.
> + description: A COMPHY lane child node
> + type: object
> + additionalProperties: false
> +
> + properties:
> + reg:
> + description: COMPHY lane number
> +
> + '#phy-cells':
> + const: 1
> +
> + required:
> + - reg
> + - '#phy-cells'
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
Thanks,
Miquèl
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
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2025-06-09 8:01 ` Miquel Raynal
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