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Wed, 4 Nov 2026 07:08:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793776092; bh=vXoloEh6FJGNcPwlC3Osvgak4yvUbh+FGNfQQluoHvM=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=ADSfcTJVFSuqx/1GtkR4HF4surfKM+BvmtmCBD0bSmQBdAC1iILVEQ7ypiyKzIs+M 2atdyy8NssQ4VpGMvGTQ2/G5ait7EFXpCUJpWSzTqKZrM81l3DqIEydZUeW8VaRuMX y4oUmMKm1qHz9wNpuXS8euqJ4bvhwJaGjQmC1ZrECnhxdhrfa/a5rpXL2AWghH+p/n wOjxryImZywVvWjbD0KKcl6AgMFKO0SaY8H7Y8Yb840NFiFMnmHw8doEEbJTk/NoMP okNAiG2A71lg2+nxThtU3CJxZG74jpmfaMbxusccqVjwv1bb8uvTDZGPCRqdN+Cl6i l8dYknklWUWmg== Message-ID: <8942bbed-cd53-44a4-8559-c18fb2073bb2@kernel.org> Date: Wed, 4 Nov 2026 08:08:04 +0100 X-Archived-By: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/5] phy: qcom-mipi-csi2: Add sc7280 D-PHY provider To: Anusha Arun Nandi , Bryan O'Donoghue Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com> <20261103214105.3605181-6-anusha.nandi@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" X-Spam-Status: No, score=-10.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 03/11/2026 22:41, Anusha Arun Nandi wrote: > Add the SC7280 CSIPHY to the generic MIPI CSI2 PHY driver, > bound to a new "qcom,sc7280-csi2-phy" compatible > and reusing the existing D-PHY 2-phase hw ops > (phy_qcom_mipi_csi2_ops_3ph_1_0). The lane_regs_sc7280[] init > sequence is the CSIPHY 5nm 2-phase 2.5Gbps 4-lane D-PHY register > set ported from the legacy in-tree camss-csiphy-3ph-1-0.c table, > with the entries that table left as do-not-program placeholders > simply omitted here rather than carried as a new marker. The > soc_cfg declares the core/timer clocks (matching x1e80100's and > sa8775p's clock-names convention for this pair) and the > vdda-phy/vdda-pll supplies. > > Like x1e80100 and SA8775P, SC7280's CSIPHY core clock is OPP-scaled > against the sensor's link frequency via the shared csiphy_opp_table > in kodiak.dtsi, so opp_clk_name is set to "core" here too. SC7280's > CSIPHY has a single power-domain, the Titan Top GDSC, matching > camss.c's sc7280_resources.pd_name = "top" and kodiak.dtsi's > existing camss node; it is not OPP-scaled, only kept enabled. > > Reviewed-by: Jigarkumar Zala Where/When? Please provide lore links and proper changelog. ... > + > +static const char * const sc7280_clks[] = { > + "core", > + "timer", > +}; What is the point of this array for each variant if all devices have the same names? IOW, what is the point of patch #2? Best regards, Krzysztof -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy