* [PATCH v2 0/2] arm64: dts: qcom: sc7280: Add PCIe0 node
@ 2025-08-12 13:56 Krishna Chaitanya Chundru
2025-08-12 13:56 ` [PATCH v2 1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document SC7280 PCIe0 phy Krishna Chaitanya Chundru
2025-08-12 13:56 ` [PATCH v2 2/2] arm64: dts: qcom: sc7280: Add PCIe0 node Krishna Chaitanya Chundru
0 siblings, 2 replies; 5+ messages in thread
From: Krishna Chaitanya Chundru @ 2025-08-12 13:56 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, cros-qcom-dts-watchers,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Krishna Chaitanya Chundru
Add PCIe dtsi node for PCIe0 controller on sc7280 platform.
SC7280 PCIe0 PHY is functionally compatible with the SM8250 Gen3 x1 PCIe
PHY. To reflect this compatibility, update the binding schema to include
qcom,sc7280-qmp-gen3x1-pcie-phy using enum within a oneOf block, while
retaining qcom,sm8250-qmp-gen3x1-pcie-phy as a const.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
Changes from v1:
- Rebased to the latest code
- Added new compatible for pcie0 phy (Krzysztof)
- Fix the name of the pinctrl state of PCIe side band signals(Krzysztof)
Link to v1: https://lore.kernel.org/all/1690540760-20191-1-git-send-email-quic_krichai@quicinc.com/
---
Krishna Chaitanya Chundru (2):
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document SC7280 PCIe0 phy
arm64: dts: qcom: sc7280: Add PCIe0 node
.../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 69 +++++----
arch/arm64/boot/dts/qcom/sc7280.dtsi | 170 ++++++++++++++++++++-
2 files changed, 206 insertions(+), 33 deletions(-)
---
base-commit: c30a13538d9f8b2a60b2f6b26abe046dea10aa12
change-id: 20250809-sc7280-2dedf8ecad04
Best regards,
--
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document SC7280 PCIe0 phy
2025-08-12 13:56 [PATCH v2 0/2] arm64: dts: qcom: sc7280: Add PCIe0 node Krishna Chaitanya Chundru
@ 2025-08-12 13:56 ` Krishna Chaitanya Chundru
2025-08-14 14:16 ` Bjorn Andersson
2025-08-12 13:56 ` [PATCH v2 2/2] arm64: dts: qcom: sc7280: Add PCIe0 node Krishna Chaitanya Chundru
1 sibling, 1 reply; 5+ messages in thread
From: Krishna Chaitanya Chundru @ 2025-08-12 13:56 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, cros-qcom-dts-watchers,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Krishna Chaitanya Chundru
SC7280 PCIe0 PHY is functionally compatible with the SM8250 Gen3 x1 PCIe
PHY. To reflect this compatibility, update the binding schema to include
qcom,sc7280-qmp-gen3x1-pcie-phy using enum within a oneOf block, while
retaining qcom,sm8250-qmp-gen3x1-pcie-phy as a const.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
.../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 69 ++++++++++++----------
1 file changed, 37 insertions(+), 32 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index a1ae8c7988c891a11f6872e58d25e9d04abb41ce..1e08e26892f7b769b75bb905377d30a301e6631c 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -15,38 +15,43 @@ description:
properties:
compatible:
- enum:
- - qcom,qcs615-qmp-gen3x1-pcie-phy
- - qcom,qcs8300-qmp-gen4x2-pcie-phy
- - qcom,sa8775p-qmp-gen4x2-pcie-phy
- - qcom,sa8775p-qmp-gen4x4-pcie-phy
- - qcom,sar2130p-qmp-gen3x2-pcie-phy
- - qcom,sc8180x-qmp-pcie-phy
- - qcom,sc8280xp-qmp-gen3x1-pcie-phy
- - qcom,sc8280xp-qmp-gen3x2-pcie-phy
- - qcom,sc8280xp-qmp-gen3x4-pcie-phy
- - qcom,sdm845-qhp-pcie-phy
- - qcom,sdm845-qmp-pcie-phy
- - qcom,sdx55-qmp-pcie-phy
- - qcom,sdx65-qmp-gen4x2-pcie-phy
- - qcom,sm8150-qmp-gen3x1-pcie-phy
- - qcom,sm8150-qmp-gen3x2-pcie-phy
- - qcom,sm8250-qmp-gen3x1-pcie-phy
- - qcom,sm8250-qmp-gen3x2-pcie-phy
- - qcom,sm8250-qmp-modem-pcie-phy
- - qcom,sm8350-qmp-gen3x1-pcie-phy
- - qcom,sm8350-qmp-gen3x2-pcie-phy
- - qcom,sm8450-qmp-gen3x1-pcie-phy
- - qcom,sm8450-qmp-gen4x2-pcie-phy
- - qcom,sm8550-qmp-gen3x2-pcie-phy
- - qcom,sm8550-qmp-gen4x2-pcie-phy
- - qcom,sm8650-qmp-gen3x2-pcie-phy
- - qcom,sm8650-qmp-gen4x2-pcie-phy
- - qcom,x1e80100-qmp-gen3x2-pcie-phy
- - qcom,x1e80100-qmp-gen4x2-pcie-phy
- - qcom,x1e80100-qmp-gen4x4-pcie-phy
- - qcom,x1e80100-qmp-gen4x8-pcie-phy
- - qcom,x1p42100-qmp-gen4x4-pcie-phy
+ oneOf:
+ - items:
+ - const: qcom,sc7280-qmp-gen3x1-pcie-phy
+ - const: qcom,sm8250-qmp-gen3x1-pcie-phy
+ - items:
+ - enum:
+ - qcom,qcs615-qmp-gen3x1-pcie-phy
+ - qcom,qcs8300-qmp-gen4x2-pcie-phy
+ - qcom,sa8775p-qmp-gen4x2-pcie-phy
+ - qcom,sa8775p-qmp-gen4x4-pcie-phy
+ - qcom,sar2130p-qmp-gen3x2-pcie-phy
+ - qcom,sc8180x-qmp-pcie-phy
+ - qcom,sc8280xp-qmp-gen3x1-pcie-phy
+ - qcom,sc8280xp-qmp-gen3x2-pcie-phy
+ - qcom,sc8280xp-qmp-gen3x4-pcie-phy
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ - qcom,sdx55-qmp-pcie-phy
+ - qcom,sdx65-qmp-gen4x2-pcie-phy
+ - qcom,sm8150-qmp-gen3x1-pcie-phy
+ - qcom,sm8150-qmp-gen3x2-pcie-phy
+ - qcom,sm8250-qmp-gen3x1-pcie-phy
+ - qcom,sm8250-qmp-gen3x2-pcie-phy
+ - qcom,sm8250-qmp-modem-pcie-phy
+ - qcom,sm8350-qmp-gen3x1-pcie-phy
+ - qcom,sm8350-qmp-gen3x2-pcie-phy
+ - qcom,sm8450-qmp-gen3x1-pcie-phy
+ - qcom,sm8450-qmp-gen4x2-pcie-phy
+ - qcom,sm8550-qmp-gen3x2-pcie-phy
+ - qcom,sm8550-qmp-gen4x2-pcie-phy
+ - qcom,sm8650-qmp-gen3x2-pcie-phy
+ - qcom,sm8650-qmp-gen4x2-pcie-phy
+ - qcom,x1e80100-qmp-gen3x2-pcie-phy
+ - qcom,x1e80100-qmp-gen4x2-pcie-phy
+ - qcom,x1e80100-qmp-gen4x4-pcie-phy
+ - qcom,x1e80100-qmp-gen4x8-pcie-phy
+ - qcom,x1p42100-qmp-gen4x4-pcie-phy
reg:
minItems: 1
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] arm64: dts: qcom: sc7280: Add PCIe0 node
2025-08-12 13:56 [PATCH v2 0/2] arm64: dts: qcom: sc7280: Add PCIe0 node Krishna Chaitanya Chundru
2025-08-12 13:56 ` [PATCH v2 1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document SC7280 PCIe0 phy Krishna Chaitanya Chundru
@ 2025-08-12 13:56 ` Krishna Chaitanya Chundru
2025-08-12 14:04 ` Krzysztof Kozlowski
1 sibling, 1 reply; 5+ messages in thread
From: Krishna Chaitanya Chundru @ 2025-08-12 13:56 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, cros-qcom-dts-watchers,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Krishna Chaitanya Chundru
Add PCIe dtsi node for PCIe0 controller on sc7280 platform.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 170 ++++++++++++++++++++++++++++++++++-
1 file changed, 169 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 64a2abd3010018e94eb50c534a509d6b4cf2473b..b0f688ce1c285888c05ed718e58dfafd51e2c1cf 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -970,7 +970,7 @@ gcc: clock-controller@100000 {
reg = <0 0x00100000 0 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
- <0>, <&pcie1_phy>,
+ <&pcie0_phy>, <&pcie1_phy>,
<&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
@@ -2200,6 +2200,149 @@ wifi: wifi@17a10040 {
qcom,smem-state-names = "wlan-smp2p-out";
};
+ pcie0: pci@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc7280";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf1d>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x1000>,
+ <0x0 0x60100000 0x0 0x100000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+ <&pcie0_phy>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
+
+ clock-names = "pipe",
+ "pipe_mux",
+ "phy_pipe",
+ "ref",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu",
+ "aggre0",
+ "aggre1";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre1_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc2 SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
+
+ status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,sc7280-qmp-gen3x1-pcie-phy", "qcom,sm8250-qmp-gen3x1-pcie-phy";
+ reg = <0 0x01c06000 0 0x1000>;
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+ };
+
pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sc7280";
reg = <0 0x01c08000 0 0x3000>,
@@ -5285,6 +5428,31 @@ mi2s1_ws: mi2s1-ws-state {
function = "mi2s1_ws";
};
+ pcie0_reset_n: pcie0-reset-n-state {
+ pins = "gpio87";
+ function = "gpio";
+
+ drive-strength = <16>;
+ output-low;
+ bias-disable;
+ };
+
+ pcie0_wake_n: pcie0-wake-n-state {
+ pins = "gpio89";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie0_clkreq_n: pcie0-clkreq-n-state {
+ pins = "gpio88";
+ function = "pcie0_clkreqn";
+
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
pcie1_clkreq_n: pcie1-clkreq-n-state {
pins = "gpio79";
function = "pcie1_clkreqn";
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: qcom: sc7280: Add PCIe0 node
2025-08-12 13:56 ` [PATCH v2 2/2] arm64: dts: qcom: sc7280: Add PCIe0 node Krishna Chaitanya Chundru
@ 2025-08-12 14:04 ` Krzysztof Kozlowski
0 siblings, 0 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2025-08-12 14:04 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
On 12/08/2025 15:56, Krishna Chaitanya Chundru wrote:
> Add PCIe dtsi node for PCIe0 controller on sc7280 platform.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 170 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 169 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 64a2abd3010018e94eb50c534a509d6b4cf2473b..b0f688ce1c285888c05ed718e58dfafd51e2c1cf 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -970,7 +970,7 @@ gcc: clock-controller@100000 {
> reg = <0 0x00100000 0 0x1f0000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> - <0>, <&pcie1_phy>,
> + <&pcie0_phy>, <&pcie1_phy>,
> <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
> <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> @@ -2200,6 +2200,149 @@ wifi: wifi@17a10040 {
> qcom,smem-state-names = "wlan-smp2p-out";
> };
>
> + pcie0: pci@1c00000 {
> + device_type = "pci";
> + compatible = "qcom,pcie-sc7280";
This was already sent and reviewed by Bjorn. Please don't duplicate the
work.
Or implement entire feedback given on that other patchset.
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document SC7280 PCIe0 phy
2025-08-12 13:56 ` [PATCH v2 1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document SC7280 PCIe0 phy Krishna Chaitanya Chundru
@ 2025-08-14 14:16 ` Bjorn Andersson
0 siblings, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2025-08-14 14:16 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, cros-qcom-dts-watchers,
Konrad Dybcio, linux-arm-msm, linux-phy, devicetree, linux-kernel
On Tue, Aug 12, 2025 at 07:26:44PM +0530, Krishna Chaitanya Chundru wrote:
> SC7280 PCIe0 PHY is functionally compatible with the SM8250 Gen3 x1 PCIe
> PHY. To reflect this compatibility, update the binding schema to include
^--- I think here would be a good place to break for a new
paragraph, to give separation between problem description and
solution description.
> qcom,sc7280-qmp-gen3x1-pcie-phy using enum within a oneOf block, while
> retaining qcom,sm8250-qmp-gen3x1-pcie-phy as a const.
>
Isn't this the case for &pcie1 as well? If so, can you please fix both?
Also, before we do that, the fact that they are "functionally
compatible", can you confirm that these two platforms really has the
same PHY settings?
Regards,
Bjorn
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 69 ++++++++++++----------
> 1 file changed, 37 insertions(+), 32 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> index a1ae8c7988c891a11f6872e58d25e9d04abb41ce..1e08e26892f7b769b75bb905377d30a301e6631c 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> @@ -15,38 +15,43 @@ description:
>
> properties:
> compatible:
> - enum:
> - - qcom,qcs615-qmp-gen3x1-pcie-phy
> - - qcom,qcs8300-qmp-gen4x2-pcie-phy
> - - qcom,sa8775p-qmp-gen4x2-pcie-phy
> - - qcom,sa8775p-qmp-gen4x4-pcie-phy
> - - qcom,sar2130p-qmp-gen3x2-pcie-phy
> - - qcom,sc8180x-qmp-pcie-phy
> - - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> - - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> - - qcom,sc8280xp-qmp-gen3x4-pcie-phy
> - - qcom,sdm845-qhp-pcie-phy
> - - qcom,sdm845-qmp-pcie-phy
> - - qcom,sdx55-qmp-pcie-phy
> - - qcom,sdx65-qmp-gen4x2-pcie-phy
> - - qcom,sm8150-qmp-gen3x1-pcie-phy
> - - qcom,sm8150-qmp-gen3x2-pcie-phy
> - - qcom,sm8250-qmp-gen3x1-pcie-phy
> - - qcom,sm8250-qmp-gen3x2-pcie-phy
> - - qcom,sm8250-qmp-modem-pcie-phy
> - - qcom,sm8350-qmp-gen3x1-pcie-phy
> - - qcom,sm8350-qmp-gen3x2-pcie-phy
> - - qcom,sm8450-qmp-gen3x1-pcie-phy
> - - qcom,sm8450-qmp-gen4x2-pcie-phy
> - - qcom,sm8550-qmp-gen3x2-pcie-phy
> - - qcom,sm8550-qmp-gen4x2-pcie-phy
> - - qcom,sm8650-qmp-gen3x2-pcie-phy
> - - qcom,sm8650-qmp-gen4x2-pcie-phy
> - - qcom,x1e80100-qmp-gen3x2-pcie-phy
> - - qcom,x1e80100-qmp-gen4x2-pcie-phy
> - - qcom,x1e80100-qmp-gen4x4-pcie-phy
> - - qcom,x1e80100-qmp-gen4x8-pcie-phy
> - - qcom,x1p42100-qmp-gen4x4-pcie-phy
> + oneOf:
> + - items:
> + - const: qcom,sc7280-qmp-gen3x1-pcie-phy
> + - const: qcom,sm8250-qmp-gen3x1-pcie-phy
> + - items:
> + - enum:
> + - qcom,qcs615-qmp-gen3x1-pcie-phy
> + - qcom,qcs8300-qmp-gen4x2-pcie-phy
> + - qcom,sa8775p-qmp-gen4x2-pcie-phy
> + - qcom,sa8775p-qmp-gen4x4-pcie-phy
> + - qcom,sar2130p-qmp-gen3x2-pcie-phy
> + - qcom,sc8180x-qmp-pcie-phy
> + - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> + - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> + - qcom,sc8280xp-qmp-gen3x4-pcie-phy
> + - qcom,sdm845-qhp-pcie-phy
> + - qcom,sdm845-qmp-pcie-phy
> + - qcom,sdx55-qmp-pcie-phy
> + - qcom,sdx65-qmp-gen4x2-pcie-phy
> + - qcom,sm8150-qmp-gen3x1-pcie-phy
> + - qcom,sm8150-qmp-gen3x2-pcie-phy
> + - qcom,sm8250-qmp-gen3x1-pcie-phy
> + - qcom,sm8250-qmp-gen3x2-pcie-phy
> + - qcom,sm8250-qmp-modem-pcie-phy
> + - qcom,sm8350-qmp-gen3x1-pcie-phy
> + - qcom,sm8350-qmp-gen3x2-pcie-phy
> + - qcom,sm8450-qmp-gen3x1-pcie-phy
> + - qcom,sm8450-qmp-gen4x2-pcie-phy
> + - qcom,sm8550-qmp-gen3x2-pcie-phy
> + - qcom,sm8550-qmp-gen4x2-pcie-phy
> + - qcom,sm8650-qmp-gen3x2-pcie-phy
> + - qcom,sm8650-qmp-gen4x2-pcie-phy
> + - qcom,x1e80100-qmp-gen3x2-pcie-phy
> + - qcom,x1e80100-qmp-gen4x2-pcie-phy
> + - qcom,x1e80100-qmp-gen4x4-pcie-phy
> + - qcom,x1e80100-qmp-gen4x8-pcie-phy
> + - qcom,x1p42100-qmp-gen4x4-pcie-phy
>
> reg:
> minItems: 1
>
> --
> 2.34.1
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-08-14 15:23 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-12 13:56 [PATCH v2 0/2] arm64: dts: qcom: sc7280: Add PCIe0 node Krishna Chaitanya Chundru
2025-08-12 13:56 ` [PATCH v2 1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document SC7280 PCIe0 phy Krishna Chaitanya Chundru
2025-08-14 14:16 ` Bjorn Andersson
2025-08-12 13:56 ` [PATCH v2 2/2] arm64: dts: qcom: sc7280: Add PCIe0 node Krishna Chaitanya Chundru
2025-08-12 14:04 ` Krzysztof Kozlowski
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).