Re: [PATCH v6 3/8] phy: Add driver for EyeQ5 Ethernet PHY wrapper

["Théo Lebrun" <theo.lebrun@bootlin.com>]

On Wed Feb 25, 2026 at 4:00 PM CET, Vinod Koul wrote:
> On 27-01-26, 18:09, Théo Lebrun wrote:
>> EyeQ5 embeds a system-controller called OLB. It features many unrelated
>> registers, and some of those are registers used to configure the
>> integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances.
>> 
>> Wrap in a neat generic PHY provider, exposing two PHYs with standard
>> phy_init() / phy_set_mode() / phy_power_on() operations.
>
> Is there a dependency of this patch with rest of the series. If not
> please post different series for subsystems.

ACK. It felt sensible to keep patches close together to understand their
reasoning.
 - clk patches are there because they imply we get a dev->of_node.
   Without them we don't and therefore the driver is useless.
 - DTS/MIPS patches are there because they exploit this new driver.
   They show the first users of this driver.

Will split for next revision.

>> +static int eq5_phy_init(struct phy *phy)
>> +{
>> +	struct eq5_phy_inst *inst = phy_get_drvdata(phy);
>> +	struct eq5_phy_private *priv = inst->priv;
>> +	struct device *dev = priv->dev;
>> +	u32 reg;
>> +
>> +	dev_dbg(dev, "phy_init(inst=%td)\n", inst - priv->phys);
>> +
>> +	writel(0, inst->gp);
>> +	writel(0, inst->sgmii);
>> +
>> +	udelay(5);
>
> This is _same_ as exit. Why not call that routine here and document
> why...

ACK!

Thanks,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


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