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Wed, 08 Feb 2023 09:10:19 -0800 (PST) Date: Wed, 8 Feb 2023 19:10:17 +0200 From: Abel Vesa To: Johan Hovold Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: Re: [PATCH v7 10/12] PCI: qcom: Add SM8550 PCIe support Message-ID: References: <20230203081807.2248625-1-abel.vesa@linaro.org> <20230203081807.2248625-11-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230208_091025_161424_703F2339 X-CRM114-Status: GOOD ( 28.58 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 23-02-08 17:40:03, Johan Hovold wrote: > On Mon, Feb 06, 2023 at 05:11:01PM +0200, Abel Vesa wrote: > > On 23-02-03 10:49:24, Johan Hovold wrote: > > > On Fri, Feb 03, 2023 at 10:18:05AM +0200, Abel Vesa wrote: > > > > Add compatible for both PCIe found on SM8550. > > > > Also add the cnoc_pcie_sf_axi clock needed by the SM8550. > > > > > > nit: You're now also adding 'noc_aggr' > > > > > > > Signed-off-by: Abel Vesa > > > > Reviewed-by: Konrad Dybcio > > > > Reviewed-by: Manivannan Sadhasivam > > > > --- > > > > > @@ -182,10 +182,10 @@ struct qcom_pcie_resources_2_3_3 { > > > > > > > > /* 6 clocks typically, 7 for sm8250 */ > > > > struct qcom_pcie_resources_2_7_0 { > > > > - struct clk_bulk_data clks[12]; > > > > + struct clk_bulk_data clks[14]; > > > > int num_clks; > > > > struct regulator_bulk_data supplies[2]; > > > > - struct reset_control *pci_reset; > > > > + struct reset_control *rst; > > > > > > Please name this one 'reset' or 'resets' (e.g. to avoid hard to parse > > > things like res->rst below). > > > > Well, it would then be inconsitent with 2_3_3 and 2_9_0, which both use > > rst. > > Yeah, I saw that. Fortunately these resources are completely > independent, but whatever. Will do it in the next version then. > > > > > }; > > > > > > > > struct qcom_pcie_resources_2_9_0 { > > > > @@ -1177,9 +1177,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > > > > unsigned int idx; > > > > int ret; > > > > > > > > - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); > > > > - if (IS_ERR(res->pci_reset)) > > > > - return PTR_ERR(res->pci_reset); > > > > + res->rst = devm_reset_control_array_get_exclusive(dev); > > > > + if (IS_ERR(res->rst)) > > > > + return PTR_ERR(res->rst); > > > > > > So the reset array implementation apparently both asserts and deasserts > > > the resets in the order specified in DT (i.e. does not deassert in > > > reverse order). > > > > > > Is that ok also for the new "pci" and "link_down" resets? > > > > According to the HPG, yes, this is perfectly fine. It specifically says > > to assert the pcie reset and then continues saying to assert the > > link_down reset. > > Ok, but that doesn't really say anything about whether it's ok to > *deassert* them in the same order, which was what I asked about. Actually, what I wanted to say is that the HPG says something like this: "assert pcie reset, then assert link_down" and then at the end it literaly repeats the same phrase. > > Johan -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy