From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C33CC54EBD for ; Fri, 13 Jan 2023 18:35:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=P5QE2YUjVsx3LOkzB4L6iWR7i9D3KXMzV9CSPoCBv2g=; b=HUKoi+S2ji1Aqm 0ogHMzgHoNtn6YHTHxtgxKkRiUBMAJgX54bCPllHJIqGk1YHV0HTJe1x70DVuNl/V2oBUp3tHcnvu IogkUWwPcbpJCzyhrd+Q9AqsPZcSyMixk9ksoTZyNO1UEMgDxUeiQqAffT4cNp0FXwSBOStNXXq32 Zax1QQU1k6Nj/t60STGAHVOdF5ujnZgDJqYlcKbAS1FC114/4c1Jh+LJ1lFasYf62VIEQA8BJgmSu 617wiaqF6PvIiE/sGwcVnzjU/M1Rrw73Iqw81KogGyGWgDh0mhrIwP6HALy4glSpw8VgLR45aB3DN kKfct2lZwFIRTpsxDJhg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGOtk-00441e-R6; Fri, 13 Jan 2023 18:35:28 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGOth-00440h-9N for linux-phy@lists.infradead.org; Fri, 13 Jan 2023 18:35:27 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id D0D71CE2124; Fri, 13 Jan 2023 18:35:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3A50DC433D2; Fri, 13 Jan 2023 18:35:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673634921; bh=7OydYNeTloaeZWCHDJulIDUJtoJ1698N16BAQwlEIkE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=CjQU7Lcv2Q7e51/Mj4meYlWwj6xx+FA8AptxpTqnpswpE55GDUvPJJl8CsHa0wFYt IzQZreiOBQDeaEhduQ0X5uqtkCF4ONHkljGljVUq7U4CnVePjU1B8b6GvYfLMDGGYW rA00/D7OxEV1oiaJAXisjskJJ6gsNT1XDPgJYBEx0aCTzslSDSeL3uQp3yR3gpCaPO UeiKnrYCxw4L3gb6hNKBgv73cjfmmmikw7Nfhix5cSzmzZla7jdhVK4hA2rWNxgmBJ GrxbO/uO3lo5G8zy3pv7SK7oBQ0d2Xeyzc081Ct82ddaUGTFKYk6ooa8PgxmLFRqLp i+ShePHg0P9gA== Date: Sat, 14 Jan 2023 00:05:16 +0530 From: Vinod Koul To: Abel Vesa , mani@kernel.org Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: Re: [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support Message-ID: References: <20230112130542.1399921-1-abel.vesa@linaro.org> <20230112130542.1399921-7-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230112130542.1399921-7-abel.vesa@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230113_103525_689250_6BEDB743 X-CRM114-Status: GOOD ( 18.63 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 12-01-23, 15:05, Abel Vesa wrote: > Add SM8550 specific register layout and table configs. Not related, but was this tested with the UFS Gear 4 support from Mani? It would be great to have that added (here or separately) > > Signed-off-by: Abel Vesa > --- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 100 ++++++++++++++++++++++++ > 1 file changed, 100 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > index 5936a3a05002..a9b666f32f59 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > @@ -95,6 +95,13 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, > }; > > +static const unsigned int sm8550_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > + [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, > + [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, > + [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, > + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, > +}; > + > static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), > @@ -599,6 +606,61 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), > }; > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), > + > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), > + > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), > + > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > +}; > + > struct qmp_ufs_offsets { > u16 serdes; > u16 pcs; > @@ -703,6 +765,10 @@ static const char * const sm8450_ufs_phy_clk_l[] = { > "qref", "ref", "ref_aux", > }; > > +static const char * const sm8550_ufs_phy_clk_l[] = { > + "qref", "ref", > +}; > + > static const char * const sdm845_ufs_phy_clk_l[] = { > "ref", "ref_aux", > }; > @@ -721,6 +787,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { > .rx2 = 0xa00, > }; > > +static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { > + .serdes = 0, > + .pcs = 0x400, > + .tx = 0x1000, > + .rx = 0x1200, > + .tx2 = 0x1800, > + .rx2 = 0x1a00, > +}; > + > static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { > .lanes = 1, > > @@ -958,6 +1033,28 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { > .regs = sm8150_ufsphy_regs_layout, > }; > > +static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { > + .lanes = 2, > + > + .offsets = &qmp_ufs_offsets_v6, > + > + .tbls = { > + .serdes = sm8550_ufsphy_serdes, > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), > + .tx = sm8550_ufsphy_tx, > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), > + .rx = sm8550_ufsphy_rx, > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), > + .pcs = sm8550_ufsphy_pcs, > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), > + }, > + .clk_list = sm8550_ufs_phy_clk_l, > + .num_clks = ARRAY_SIZE(sm8550_ufs_phy_clk_l), > + .vreg_list = qmp_phy_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > + .regs = sm8550_ufsphy_regs_layout, > +}; > + > static void qmp_ufs_configure_lane(void __iomem *base, > const struct qmp_phy_init_tbl tbl[], > int num, > @@ -1467,6 +1564,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { > }, { > .compatible = "qcom,sm8450-qmp-ufs-phy", > .data = &sm8450_ufsphy_cfg, > + }, { > + .compatible = "qcom,sm8550-qmp-ufs-phy", > + .data = &sm8550_ufsphy_cfg, > }, > { }, > }; > -- > 2.34.1 -- ~Vinod -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy