From: Thierry Reding <thierry.reding@gmail.com>
To: Vinod Koul <vkoul@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Mathias Nyman <mathias.nyman@intel.com>,
JC Kuo <jckuo@nvidia.com>, Jon Hunter <jonathanh@nvidia.com>,
linux-tegra@vger.kernel.org, linux-phy@lists.infradead.org,
linux-usb@vger.kernel.org
Subject: Re: [PATCH v8 03/13] phy: tegra: xusb: Move usb3 port init for Tegra210
Date: Wed, 31 Mar 2021 18:32:01 +0200 [thread overview]
Message-ID: <YGSkAcRLByY8zNnu@orome.fritz.box> (raw)
In-Reply-To: <YGMx5cLmX+d48XKO@vkoul-mobl.Dlink>
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On Tue, Mar 30, 2021 at 07:42:53PM +0530, Vinod Koul wrote:
> Hi Thierry,
>
> On 25-03-21, 17:40, Thierry Reding wrote:
>
> > +static struct tegra_xusb_usb3_port *
> > +tegra210_lane_to_usb3_port(struct tegra_xusb_lane *lane)
> > +{
> > + int port;
> > +
> > + if (!lane || !lane->pad || !lane->pad->padctl)
> > + return NULL;
>
> This looks problematic to me, so if lane is NULL, it will still go ahead
> and check lane->pad which would result in NULL pointer dereference.
No, this isn't going to result in a NULL pointer dereference because the
compiler will short-circuit this if the first expression is true. If the
lane parameter is NULL, then the entire expression is going to be true
no matter what lane->pad and lane->pad->padctl evaluate to (because of
the logical OR) and hence the compiler knows that it can skip the rest.
This is a fairly common construct in kernel code.
Thierry
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next prev parent reply other threads:[~2021-03-31 16:31 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-25 16:40 [PATCH v8 00/13] Tegra XHCI controller ELPG support Thierry Reding
2021-03-25 16:40 ` [PATCH v8 01/13] clk: tegra: Add PLLE HW power sequencer control Thierry Reding
2021-03-25 16:40 ` [PATCH v8 02/13] clk: tegra: Don't enable PLLE HW sequencer at init Thierry Reding
2021-03-25 16:40 ` [PATCH v8 03/13] phy: tegra: xusb: Move usb3 port init for Tegra210 Thierry Reding
2021-03-30 14:12 ` Vinod Koul
2021-03-31 16:32 ` Thierry Reding [this message]
2021-04-01 5:15 ` Vinod Koul
2021-03-25 16:40 ` [PATCH v8 04/13] phy: tegra: xusb: Rearrange UPHY init on Tegra210 Thierry Reding
2021-03-30 14:20 ` Vinod Koul
2021-03-25 16:40 ` [PATCH v8 05/13] phy: tegra: xusb: Add Tegra210 lane_iddq operation Thierry Reding
2021-03-30 14:21 ` Vinod Koul
2021-03-31 16:36 ` Thierry Reding
2021-03-25 16:40 ` [PATCH v8 06/13] phy: tegra: xusb: Add sleepwalk and suspend/resume Thierry Reding
2021-03-30 14:23 ` Vinod Koul
2021-03-31 16:38 ` Thierry Reding
2021-03-31 16:45 ` Thierry Reding
2021-03-31 16:52 ` Thierry Reding
2021-03-25 16:40 ` [PATCH v8 07/13] soc/tegra: pmc: Provide USB sleepwalk register map Thierry Reding
2021-03-25 16:40 ` [PATCH v8 08/13] dt-bindings: phy: tegra-xusb: Add nvidia,pmc prop Thierry Reding
2021-03-25 16:40 ` [PATCH v8 09/13] phy: tegra: xusb: Add wake/sleepwalk for Tegra210 Thierry Reding
2021-03-25 20:26 ` Nathan Chancellor
2021-03-26 12:44 ` Thierry Reding
2021-04-01 6:45 ` Vinod Koul
2021-04-01 10:44 ` Thierry Reding
2021-04-01 11:05 ` [PATCH v9 " Thierry Reding
2021-04-06 5:01 ` Vinod Koul
2021-04-06 13:58 ` Thierry Reding
2021-04-11 14:30 ` Vinod Koul
2021-03-25 16:40 ` [PATCH v8 10/13] phy: tegra: xusb: Tegra210 host mode VBUS control Thierry Reding
2021-04-01 6:45 ` Vinod Koul
2021-03-25 16:40 ` [PATCH v8 11/13] phy: tegra: xusb: Add wake/sleepwalk for Tegra186 Thierry Reding
2021-04-01 6:49 ` Vinod Koul
2021-04-01 11:00 ` Thierry Reding
2021-03-25 16:40 ` [PATCH v8 12/13] usb: host: xhci-tegra: Unlink power domain devices Thierry Reding
2021-03-25 16:40 ` [PATCH v8 13/13] xhci: tegra: Enable ELPG for runtime/system PM Thierry Reding
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