From: Vinod Koul <vkoul@kernel.org>
To: Stephen Boyd <swboyd@chromium.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Doug Anderson <dianders@chromium.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Matthias Kaehlcke <mka@chromium.org>,
Sandeep Maheswaram <quic_c_sanm@quicinc.com>,
Wesley Cheng <wcheng@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org, quic_pkondeti@quicinc.com,
quic_ppratap@quicinc.com
Subject: Re: [PATCH] phy: qcom-snps: Correct the FSEL_MASK
Date: Thu, 21 Oct 2021 23:16:31 +0530 [thread overview]
Message-ID: <YXGndzeN/nVJp8A/@matsya> (raw)
In-Reply-To: <CAE-0n51miQBAO2QBtHG75cB4TZnm9jiXFz3APBwrNbQcfjB-Eg@mail.gmail.com>
On 21-10-21, 10:35, Stephen Boyd wrote:
> Quoting Sandeep Maheswaram (2021-10-19 23:36:25)
> > The FSEL_MASK which selects the refclock is defined incorrectly.
> > It should be [4:6] not [5:7]. Due to this incorrect definition, the BIT(7)
> > in USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 is reset which keeps PHY analog
> > blocks ON during suspend.
> > Fix this issue by correctly defining the FSEL_MASK.
> >
> > Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com>
>
> Any Fixes tag?
Yes pls add
>
> > ---
> > drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
> > index ae4bac0..28459a1 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
> > @@ -1,6 +1,7 @@
> > // SPDX-License-Identifier: GPL-2.0
> > /*
> > * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> > + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
>
> I never thought I'd see this again! :)
Also, is it justified adding a new copyright for single code line change..?
> > */
> >
> > #include <linux/clk.h>
> > @@ -33,7 +34,7 @@
> >
> > #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
> > #define RETENABLEN BIT(3)
> > -#define FSEL_MASK GENMASK(7, 5)
> > +#define FSEL_MASK GENMASK(6, 4)
> > #define FSEL_DEFAULT (0x3 << 4)
> >
> > #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
--
~Vinod
--
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prev parent reply other threads:[~2021-10-21 17:46 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 6:36 [PATCH] phy: qcom-snps: Correct the FSEL_MASK Sandeep Maheswaram
2021-10-21 17:35 ` Stephen Boyd
2021-10-21 17:46 ` Vinod Koul [this message]
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