From: Vinod Koul <vkoul@kernel.org>
To: Robert Hancock <robert.hancock@calian.com>
Cc: linux-phy@lists.infradead.org, anurag.kumar.vulisha@xilinx.com,
laurent.pinchart@ideasonboard.com, kishon@ti.com,
michal.simek@xilinx.com
Subject: Re: [PATCH] phy: xilinx: zynqmp: Fix bus width setting for SGMII
Date: Thu, 27 Jan 2022 10:55:34 +0530 [thread overview]
Message-ID: <YfIszlhQ6YARCyaW@matsya> (raw)
In-Reply-To: <20220126001600.1592218-1-robert.hancock@calian.com>
On 25-01-22, 18:16, Robert Hancock wrote:
> TX_PROT_BUS_WIDTH and RX_PROT_BUS_WIDTH are single registers with
> separate bit fields for each lane. The code in xpsgtr_phy_init_sgmii was
> not preserving the existing register value for other lanes, so enabling
> the PHY in SGMII mode on one lane zeroed out the settings for all other
> lanes, causing other PS-GTR peripherals such as USB3 to malfunction.
>
> Use xpsgtr_clr_set to only manipulate the desired bits in the register.
Applied, thanks
--
~Vinod
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prev parent reply other threads:[~2022-01-27 5:25 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 0:16 [PATCH] phy: xilinx: zynqmp: Fix bus width setting for SGMII Robert Hancock
2022-01-26 0:26 ` Laurent Pinchart
2022-01-26 7:26 ` Michal Simek
2022-01-27 5:25 ` Vinod Koul [this message]
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