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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id k22-20020a056870959600b000d277c48d18sm9802811oao.3.2022.03.29.15.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 15:58:16 -0700 (PDT) Received: (nullmailer pid 1505955 invoked by uid 1000); Tue, 29 Mar 2022 22:58:15 -0000 Date: Tue, 29 Mar 2022 17:58:15 -0500 From: Rob Herring To: Guillaume Ranquet Cc: airlied@linux.ie, angelogioacchino.delregno@collabora.com, chunfeng.yun@mediatek.com, chunkuang.hu@kernel.org, ck.hu@mediatek.com, daniel@ffwll.ch, deller@gmx.de, jitao.shi@mediatek.com, kishon@ti.com, krzk+dt@kernel.org, maarten.lankhorst@linux.intel.com, matthias.bgg@gmail.com, mripard@kernel.org, p.zabel@pengutronix.de, tzimmermann@suse.de, vkoul@kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, markyacoub@google.com Subject: Re: [PATCH v9 03/22] dt-bindings: mediatek,dp_phy: Add Display Port PHY binding Message-ID: References: <20220327223927.20848-1-granquet@baylibre.com> <20220327223927.20848-4-granquet@baylibre.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220327223927.20848-4-granquet@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220329_155818_506126_142AF407 X-CRM114-Status: GOOD ( 17.43 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Mon, Mar 28, 2022 at 12:39:08AM +0200, Guillaume Ranquet wrote: > This phy controller is embedded in the Display Port Controller on mt8195 SoCs. Sorry, but I think you need to go back to what you had in v8. While yes, the phy and controller IP often do change independently, this h/w looks pretty interwined. You could make the controller a phy provider to itself if you wanted. > > Signed-off-by: Guillaume Ranquet > --- > .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml > new file mode 100644 > index 000000000000..1f5ffca4e140 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml > @@ -0,0 +1,43 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2022 MediaTek > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Display Port PHY > + > +maintainers: > + - CK Hu > + - Jitao shi > + > +description: | > + Device tree bindings for the Mediatek (embedded) Display Port PHY > + present on some Mediatek SoCs. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8195-dp-phy > + > + mediatek,dp-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Phandle to the Display Port node. > + > + "#phy-cells": > + const: 0 > + > +required: > + - compatible > + - mediatek,dp-syscon > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + dp_phy: dp-phy { > + compatible = "mediatek,mt8195-dp-phy"; > + mediatek,dp-syscon = <&dp_tx>; > + #phy-cells = <0>; > + }; > -- > 2.34.1 > > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy