* [PATCH v4 1/6] dt-bindings: phy: Add FSD UFS PHY bindings
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
@ 2022-06-10 10:41 ` Alim Akhtar
2022-06-10 10:41 ` [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata Alim Akhtar
` (7 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Alim Akhtar @ 2022-06-10 10:41 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-scsi, linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey,
Alim Akhtar, Bharat Uppal
Add tesla,fsd-ufs-phy compatible for Tesla Full Self-Driving (FSD) SoC.
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index 17897a3b5c9e..8da99461e817 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -17,6 +17,7 @@ properties:
enum:
- samsung,exynos7-ufs-phy
- samsung,exynosautov9-ufs-phy
+ - tesla,fsd-ufs-phy
reg:
maxItems: 1
--
2.25.1
--
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
2022-06-10 10:41 ` [PATCH v4 1/6] dt-bindings: phy: Add FSD UFS PHY bindings Alim Akhtar
@ 2022-06-10 10:41 ` Alim Akhtar
2022-06-13 7:04 ` Chanho Park
2022-06-13 9:46 ` Krzysztof Kozlowski
2022-06-10 10:41 ` [PATCH v4 3/6] phy: samsung-ufs: add support for FSD ufs phy driver Alim Akhtar
` (6 subsequent siblings)
8 siblings, 2 replies; 15+ messages in thread
From: Alim Akhtar @ 2022-06-10 10:41 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-scsi, linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey,
Alim Akhtar, Bharat Uppal
Move CDR lock offset to drv data so that it can be extended for other SoCs
which are having CDR lock at different register offset.
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/phy/samsung/phy-exynos7-ufs.c | 3 +++
drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
drivers/phy/samsung/phy-samsung-ufs.c | 4 +++-
drivers/phy/samsung/phy-samsung-ufs.h | 2 +-
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
index d1e9d0ae5c1d..72854336f59d 100644
--- a/drivers/phy/samsung/phy-exynos7-ufs.c
+++ b/drivers/phy/samsung/phy-exynos7-ufs.c
@@ -11,6 +11,8 @@
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
+
/* Calibration for phy initialization */
static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
@@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
.en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
},
.has_symbol_clk = 1,
+ .cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
};
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index fa4d2983eec6..2b256070d657 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -10,6 +10,7 @@
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
#define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
@@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
.en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
},
.has_symbol_clk = 0,
+ .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 206a79c69a6c..8cec7652b459 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
}
err = readl_poll_timeout(
- ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+ ufs_phy->reg_pma +
+ PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
if (err)
dev_err(ufs_phy->dev,
@@ -327,6 +328,7 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
drvdata = match->data;
phy->dev = dev;
+ phy->drvdata = drvdata;
phy->cfgs = drvdata->cfgs;
phy->has_symbol_clk = drvdata->has_symbol_clk;
memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol));
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 854b53bdf347..913542ebff7a 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -40,7 +40,6 @@
/* UFS PHY registers */
#define PHY_PLL_LOCK_STATUS 0x1e
-#define PHY_CDR_LOCK_STATUS 0x5e
#define PHY_PLL_LOCK_BIT BIT(5)
#define PHY_CDR_LOCK_BIT BIT(4)
@@ -111,6 +110,7 @@ struct samsung_ufs_phy_drvdata {
const struct samsung_ufs_phy_cfg **cfgs;
struct samsung_ufs_phy_pmu_isol isol;
bool has_symbol_clk;
+ u32 cdr_lock_status_offset;
};
struct samsung_ufs_phy {
--
2.25.1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 15+ messages in thread* RE: [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata
2022-06-10 10:41 ` [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata Alim Akhtar
@ 2022-06-13 7:04 ` Chanho Park
2022-06-13 9:46 ` Krzysztof Kozlowski
1 sibling, 0 replies; 15+ messages in thread
From: Chanho Park @ 2022-06-13 7:04 UTC (permalink / raw)
To: 'Alim Akhtar', linux-arm-kernel, linux-kernel, linux-scsi,
linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, pankaj.dubey, 'Bharat Uppal'
> Subject: [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata
>
> Move CDR lock offset to drv data so that it can be extended for other SoCs
> which are having CDR lock at different register offset.
>
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Reviewed-by: Chanho Park <chanho61.park@samsung.com>
- Reviewed-by: Chanho Park <chanho61.park@samsung.com>
> ---
> drivers/phy/samsung/phy-exynos7-ufs.c | 3 +++
> drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
> drivers/phy/samsung/phy-samsung-ufs.c | 4 +++-
> drivers/phy/samsung/phy-samsung-ufs.h | 2 +-
> 4 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c
> b/drivers/phy/samsung/phy-exynos7-ufs.c
> index d1e9d0ae5c1d..72854336f59d 100644
> --- a/drivers/phy/samsung/phy-exynos7-ufs.c
> +++ b/drivers/phy/samsung/phy-exynos7-ufs.c
> @@ -11,6 +11,8 @@
> #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
> #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
>
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
> +
> /* Calibration for phy initialization */ static const struct
> samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
> PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), @@ -74,4 +76,5 @@
> const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
> .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
> },
> .has_symbol_clk = 1,
> + .cdr_lock_status_offset =
> EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
> };
> diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c
> b/drivers/phy/samsung/phy-exynosautov9-ufs.c
> index fa4d2983eec6..2b256070d657 100644
> --- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
> +++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
> @@ -10,6 +10,7 @@
> #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728
> #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
> #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
> +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
>
> #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
> PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) @@ -64,4 +65,5 @@ const
> struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
> .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
> },
> .has_symbol_clk = 0,
> + .cdr_lock_status_offset =
> +EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
> };
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c
> b/drivers/phy/samsung/phy-samsung-ufs.c
> index 206a79c69a6c..8cec7652b459 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.c
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy
> *phy)
> }
>
> err = readl_poll_timeout(
> - ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
> + ufs_phy->reg_pma +
> + PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
> val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
> if (err)
> dev_err(ufs_phy->dev,
> @@ -327,6 +328,7 @@ static int samsung_ufs_phy_probe(struct
> platform_device *pdev)
>
> drvdata = match->data;
> phy->dev = dev;
> + phy->drvdata = drvdata;
This can be reversing changes of below patch.
https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git/commit/?h=next&id=f86c1d0a58b1f63a176f537e2f6851be49c20ad4
By suggestion of Krzysztof, I removed drvdata assignment to samsung_ufs_phy struct and moved has_symbol_clk from drvdata to samsung_ufs_phy struct.
However, I forgot to remove drvdata from samsung_ufs_phy struct...
Anyway, you want to get back the drvdata, you may need to add a preceding patch with reconsideration of has_symbol_clk to the drvdata again.
Otherwise, you can simply put cdr_lock_status_offset to the samsung_ufs_phy struct and assign the data from drvdata same as has_symbol_clk and isol.
Best Regards,
Chanho Park
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata
2022-06-10 10:41 ` [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata Alim Akhtar
2022-06-13 7:04 ` Chanho Park
@ 2022-06-13 9:46 ` Krzysztof Kozlowski
1 sibling, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-13 9:46 UTC (permalink / raw)
To: Alim Akhtar, linux-arm-kernel, linux-kernel, linux-scsi,
linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey,
Bharat Uppal
On 10/06/2022 12:41, Alim Akhtar wrote:
> Move CDR lock offset to drv data so that it can be extended for other SoCs
> which are having CDR lock at different register offset.
>
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v4 3/6] phy: samsung-ufs: add support for FSD ufs phy driver
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
2022-06-10 10:41 ` [PATCH v4 1/6] dt-bindings: phy: Add FSD UFS PHY bindings Alim Akhtar
2022-06-10 10:41 ` [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata Alim Akhtar
@ 2022-06-10 10:41 ` Alim Akhtar
2022-06-13 9:47 ` Krzysztof Kozlowski
2022-06-10 10:41 ` [PATCH v4 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible Alim Akhtar
` (5 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Alim Akhtar @ 2022-06-10 10:41 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-scsi, linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey,
Alim Akhtar, Bharat Uppal
Adds support for Tesla Full Self-Driving (FSD) ufs phy driver.
This SoC has different cdr lock status offset.
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-fsd-ufs.c | 58 +++++++++++++++++++++++++++
drivers/phy/samsung/phy-samsung-ufs.c | 3 ++
drivers/phy/samsung/phy-samsung-ufs.h | 1 +
4 files changed, 63 insertions(+)
create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index 65e4cc59403f..afb34a153e34 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o
phy-exynos-ufs-y += phy-samsung-ufs.o
phy-exynos-ufs-y += phy-exynos7-ufs.o
phy-exynos-ufs-y += phy-exynosautov9-ufs.o
+phy-exynos-ufs-y += phy-fsd-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
new file mode 100644
index 000000000000..c78b6c16027d
--- /dev/null
+++ b/drivers/phy/samsung/phy-fsd-ufs.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver data for FSD SoC
+ *
+ * Copyright (C) 2022 Samsung Electronics Co., Ltd.
+ *
+ */
+#include "phy-samsung-ufs.h"
+
+#define FSD_EMBEDDED_COMBO_PHY_CTRL 0x724
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x6e
+
+static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B atfer PMC */
+static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {
+ [CFG_PRE_INIT] = fsd_pre_init_cfg,
+ [CFG_PRE_PWR_HS] = fsd_pre_pwr_hs_cfg,
+ [CFG_POST_PWR_HS] = fsd_post_pwr_hs_cfg,
+};
+
+const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
+ .cfgs = fsd_ufs_phy_cfgs,
+ .isol = {
+ .offset = FSD_EMBEDDED_COMBO_PHY_CTRL,
+ .mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,
+ .en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,
+ },
+ .has_symbol_clk = 0,
+ .cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 8cec7652b459..e4334529ffbc 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -358,6 +358,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = {
}, {
.compatible = "samsung,exynosautov9-ufs-phy",
.data = &exynosautov9_ufs_phy,
+ }, {
+ .compatible = "tesla,fsd-ufs-phy",
+ .data = &fsd_ufs_phy,
},
{},
};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 913542ebff7a..6320ac852f29 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -145,5 +145,6 @@ static inline void samsung_ufs_phy_ctrl_isol(
extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
+extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
#endif /* _PHY_SAMSUNG_UFS_ */
--
2.25.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v4 3/6] phy: samsung-ufs: add support for FSD ufs phy driver
2022-06-10 10:41 ` [PATCH v4 3/6] phy: samsung-ufs: add support for FSD ufs phy driver Alim Akhtar
@ 2022-06-13 9:47 ` Krzysztof Kozlowski
0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-13 9:47 UTC (permalink / raw)
To: Alim Akhtar, linux-arm-kernel, linux-kernel, linux-scsi,
linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey,
Bharat Uppal
On 10/06/2022 12:41, Alim Akhtar wrote:
> Adds support for Tesla Full Self-Driving (FSD) ufs phy driver.
> This SoC has different cdr lock status offset.
>
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v4 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
` (2 preceding siblings ...)
2022-06-10 10:41 ` [PATCH v4 3/6] phy: samsung-ufs: add support for FSD ufs phy driver Alim Akhtar
@ 2022-06-10 10:41 ` Alim Akhtar
2022-06-10 10:41 ` [PATCH v4 5/6] ufs: host: ufs-exynos: add mphy apb clock mask Alim Akhtar
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Alim Akhtar @ 2022-06-10 10:41 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-scsi, linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey,
Alim Akhtar, Bharat Uppal
Adds tesla,fsd-ufs compatible for Tesla FSD SoC.
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index c949eb617313..2c715eec48b8 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -21,6 +21,7 @@ properties:
- samsung,exynos7-ufs
- samsung,exynosautov9-ufs
- samsung,exynosautov9-ufs-vh
+ - tesla,fsd-ufs
reg:
items:
--
2.25.1
--
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v4 5/6] ufs: host: ufs-exynos: add mphy apb clock mask
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
` (3 preceding siblings ...)
2022-06-10 10:41 ` [PATCH v4 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible Alim Akhtar
@ 2022-06-10 10:41 ` Alim Akhtar
2022-06-13 9:47 ` Krzysztof Kozlowski
2022-06-10 10:41 ` [PATCH v4 6/6] ufs: host: ufs-exynos: add support for fsd ufs hci Alim Akhtar
` (3 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Alim Akhtar @ 2022-06-10 10:41 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-scsi, linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey,
Alim Akhtar
Bit[3] of HCI_CLKSTOP_CTRL register is for enabling/disabling MPHY APB
clock. Lets add it to CLK_STOP_MASK, so that the same can be controlled
during clock masking/unmasking.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Tested-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/ufs/host/ufs-exynos.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index a81d8cbd542f..cc128aff8871 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -52,11 +52,12 @@
#define HCI_ERR_EN_DME_LAYER 0x88
#define HCI_CLKSTOP_CTRL 0xB0
#define REFCLKOUT_STOP BIT(4)
+#define MPHY_APBCLK_STOP BIT(3)
#define REFCLK_STOP BIT(2)
#define UNIPRO_MCLK_STOP BIT(1)
#define UNIPRO_PCLK_STOP BIT(0)
#define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
- UNIPRO_MCLK_STOP |\
+ UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
UNIPRO_PCLK_STOP)
#define HCI_MISC 0xB4
#define REFCLK_CTRL_EN BIT(7)
--
2.25.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v4 5/6] ufs: host: ufs-exynos: add mphy apb clock mask
2022-06-10 10:41 ` [PATCH v4 5/6] ufs: host: ufs-exynos: add mphy apb clock mask Alim Akhtar
@ 2022-06-13 9:47 ` Krzysztof Kozlowski
0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-13 9:47 UTC (permalink / raw)
To: Alim Akhtar, linux-arm-kernel, linux-kernel, linux-scsi,
linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey
On 10/06/2022 12:41, Alim Akhtar wrote:
> Bit[3] of HCI_CLKSTOP_CTRL register is for enabling/disabling MPHY APB
> clock. Lets add it to CLK_STOP_MASK, so that the same can be controlled
> during clock masking/unmasking.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Reviewed-by: Chanho Park <chanho61.park@samsung.com>
> Tested-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v4 6/6] ufs: host: ufs-exynos: add support for fsd ufs hci
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
` (4 preceding siblings ...)
2022-06-10 10:41 ` [PATCH v4 5/6] ufs: host: ufs-exynos: add mphy apb clock mask Alim Akhtar
@ 2022-06-10 10:41 ` Alim Akhtar
2022-06-13 6:54 ` Chanho Park
2022-06-14 16:13 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
` (2 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Alim Akhtar @ 2022-06-10 10:41 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-scsi, linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey,
Alim Akhtar, Bharat Uppal
Adds support of UFS HCI which is found in Tesla Full Self-Driving (FSD)
SoC.
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/ufs/host/ufs-exynos.c | 140 ++++++++++++++++++++++++++++++++++
drivers/ufs/host/ufs-exynos.h | 1 +
2 files changed, 141 insertions(+)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index cc128aff8871..69943069093a 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -146,6 +146,10 @@ enum {
#define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER1 0x0A8
#define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER2 0x0AC
+#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8
+#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC
+#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0
+
/*
* UFS Protector registers
*/
@@ -1474,6 +1478,99 @@ static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
return 0;
}
+static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ int i;
+ struct ufs_hba *hba = ufs->hba;
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
+ DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+ for_each_ufs_tx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i),
+ DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
+ }
+
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
+ DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
+ }
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
+
+ exynos_ufs_establish_connt(ufs);
+
+ return 0;
+}
+
+static int fsd_ufs_post_link(struct exynos_ufs *ufs)
+{
+ int i;
+ struct ufs_hba *hba = ufs->hba;
+ u32 hw_cap_min_tactivate;
+ u32 peer_rx_min_actv_time_cap;
+ u32 max_rx_hibern8_time_cap;
+
+ ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
+ &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
+ &peer_rx_min_actv_time_cap); /* PA_TActivate */
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
+ &max_rx_hibern8_time_cap); /* PA_Hibern8Time */
+
+ if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
+ ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
+ peer_rx_min_actv_time_cap + 1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
+ }
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+
+ return 0;
+}
+
+static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+ struct ufs_pa_layer_attr *pwr)
+{
+ struct ufs_hba *hba = ufs->hba;
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
+
+ unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
+ unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
+ unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
+
+ return 0;
+}
+
static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
.name = "exynos_ufs",
.init = exynos_ufs_init,
@@ -1596,6 +1693,47 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
.post_pwr_change = exynos7_ufs_post_pwr_change,
};
+static struct exynos_ufs_uic_attr fsd_uic_attr = {
+ .tx_trailingclks = 0x10,
+ .tx_dif_p_nsec = 3000000, /* unit: ns */
+ .tx_dif_n_nsec = 1000000, /* unit: ns */
+ .tx_high_z_cnt_nsec = 20000, /* unit: ns */
+ .tx_base_unit_nsec = 100000, /* unit: ns */
+ .tx_gran_unit_nsec = 4000, /* unit: ns */
+ .tx_sleep_cnt = 1000, /* unit: ns */
+ .tx_min_activatetime = 0xa,
+ .rx_filler_enable = 0x2,
+ .rx_dif_p_nsec = 1000000, /* unit: ns */
+ .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
+ .rx_base_unit_nsec = 100000, /* unit: ns */
+ .rx_gran_unit_nsec = 4000, /* unit: ns */
+ .rx_sleep_cnt = 1280, /* unit: ns */
+ .rx_stall_cnt = 320, /* unit: ns */
+ .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
+ .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
+ .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
+ .pa_dbg_option_suite = 0x2E820183,
+};
+
+struct exynos_ufs_drv_data fsd_ufs_drvs = {
+ .uic_attr = &fsd_uic_attr,
+ .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
+ UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+ UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
+ .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
+ EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+ EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+ EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+ .pre_link = fsd_ufs_pre_link,
+ .post_link = fsd_ufs_post_link,
+ .pre_pwr_change = fsd_ufs_pre_pwr_change,
+};
+
static const struct of_device_id exynos_ufs_of_match[] = {
{ .compatible = "samsung,exynos7-ufs",
.data = &exynos_ufs_drvs },
@@ -1603,6 +1741,8 @@ static const struct of_device_id exynos_ufs_of_match[] = {
.data = &exynosauto_ufs_drvs },
{ .compatible = "samsung,exynosautov9-ufs-vh",
.data = &exynosauto_ufs_vh_drvs },
+ { .compatible = "tesla,fsd-ufs",
+ .data = &fsd_ufs_drvs },
{},
};
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index 0b0a3d530ca6..a4bd6646d7f1 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -22,6 +22,7 @@
#define PA_DBG_RXPHY_CFGUPDT 0x9519
#define PA_DBG_MODE 0x9529
#define PA_DBG_SKIP_RESET_PHY 0x9539
+#define PA_DBG_AUTOMODE_THLD 0x9536
#define PA_DBG_OV_TM 0x9540
#define PA_DBG_SKIP_LINE_RESET 0x9541
#define PA_DBG_LINE_RESET_REQ 0x9543
--
2.25.1
--
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^ permalink raw reply related [flat|nested] 15+ messages in thread* RE: [PATCH v4 6/6] ufs: host: ufs-exynos: add support for fsd ufs hci
2022-06-10 10:41 ` [PATCH v4 6/6] ufs: host: ufs-exynos: add support for fsd ufs hci Alim Akhtar
@ 2022-06-13 6:54 ` Chanho Park
0 siblings, 0 replies; 15+ messages in thread
From: Chanho Park @ 2022-06-13 6:54 UTC (permalink / raw)
To: 'Alim Akhtar', linux-arm-kernel, linux-kernel, linux-scsi,
linux-phy
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, vkoul, avri.altman,
bvanassche, martin.petersen, pankaj.dubey, 'Bharat Uppal'
> Subject: [PATCH v4 6/6] ufs: host: ufs-exynos: add support for fsd ufs hci
>
> Adds support of UFS HCI which is found in Tesla Full Self-Driving (FSD)
> SoC.
>
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Best Regards,
Chanho Park
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^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v4 0/6] Add support for UFS controller found in FSD SoC
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
` (5 preceding siblings ...)
2022-06-10 10:41 ` [PATCH v4 6/6] ufs: host: ufs-exynos: add support for fsd ufs hci Alim Akhtar
@ 2022-06-14 16:13 ` Alim Akhtar
2022-06-17 0:18 ` Vinod Koul
2022-06-17 2:21 ` Martin K. Petersen
8 siblings, 0 replies; 15+ messages in thread
From: Alim Akhtar @ 2022-06-14 16:13 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-scsi, linux-phy, vkoul
Cc: devicetree, robh+dt, krzysztof.kozlowski+dt, avri.altman,
bvanassche, martin.petersen, chanho61.park, pankaj.dubey
Hi Vinod
>-----Original Message-----
>From: Alim Akhtar [mailto:alim.akhtar@samsung.com]
>Sent: Friday, June 10, 2022 4:11 PM
>To: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>chanho61.park@samsung.com; pankaj.dubey@samsung.com; Alim Akhtar
><alim.akhtar@samsung.com>
>Subject: [PATCH v4 0/6] Add support for UFS controller found in FSD SoC
>
>
>This series adds support for UFS controller found in FSD SoC.
>The HCI is almost same as found on other Exynos SoCs with minor differences.
>This also adds the required UFS-PHY driver changes.
>
>Patch 2/6: common change to handle different CDR offsets
>
>*Changes since v3:
>- Addressed review comments on patch 6/6 from Chanho
>
>*Changes since v2:
>- Addressed review comments from Chanho
>- collected reviewed-by, tested-by tags
>- rebased on next-20220609
>
>*Changes since v1:
>- Addressed review comments from Bart, Krzysztof, Chanho
>- collected Ack-by tags
>- rebased on next-20220602
>
>
>Alim Akhtar (6):
> dt-bindings: phy: Add FSD UFS PHY bindings
> phy: samsung-ufs: move cdr offset to drvdata
> phy: samsung-ufs: add support for FSD ufs phy driver
Can you please take patch-{1/6, 2/6 and 3/6} via phy tree?
The UFS patches has been picked by Martin via SCSI tree.
Thanks.
> dt-bindings: ufs: exynos-ufs: add fsd compatible
> ufs: host: ufs-exynos: add mphy apb clock mask
> ufs: host: ufs-exynos: add support for fsd ufs hci
>
> .../bindings/phy/samsung,ufs-phy.yaml | 1 +
> .../bindings/ufs/samsung,exynos-ufs.yaml | 1 +
> drivers/phy/samsung/Makefile | 1 +
> drivers/phy/samsung/phy-exynos7-ufs.c | 3 +
> drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 +
> drivers/phy/samsung/phy-fsd-ufs.c | 58 +++++++
> drivers/phy/samsung/phy-samsung-ufs.c | 7 +-
> drivers/phy/samsung/phy-samsung-ufs.h | 3 +-
> drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++-
> drivers/ufs/host/ufs-exynos.h | 1 +
> 10 files changed, 217 insertions(+), 3 deletions(-) create mode 100644
>drivers/phy/samsung/phy-fsd-ufs.c
>
>
>base-commit: ff539ac73ea559a8c146d99ab14bfcaddd30547a
>--
>2.25.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v4 0/6] Add support for UFS controller found in FSD SoC
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
` (6 preceding siblings ...)
2022-06-14 16:13 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
@ 2022-06-17 0:18 ` Vinod Koul
2022-06-17 2:21 ` Martin K. Petersen
8 siblings, 0 replies; 15+ messages in thread
From: Vinod Koul @ 2022-06-17 0:18 UTC (permalink / raw)
To: Alim Akhtar
Cc: linux-arm-kernel, linux-kernel, linux-scsi, linux-phy, devicetree,
robh+dt, krzysztof.kozlowski+dt, avri.altman, bvanassche,
martin.petersen, chanho61.park, pankaj.dubey
On 10-06-22, 16:11, Alim Akhtar wrote:
>
> This series adds support for UFS controller found in FSD SoC.
> The HCI is almost same as found on other Exynos SoCs with minor
> differences. This also adds the required UFS-PHY driver changes.
Applied 1-3, thanks
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v4 0/6] Add support for UFS controller found in FSD SoC
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
` (7 preceding siblings ...)
2022-06-17 0:18 ` Vinod Koul
@ 2022-06-17 2:21 ` Martin K. Petersen
8 siblings, 0 replies; 15+ messages in thread
From: Martin K. Petersen @ 2022-06-17 2:21 UTC (permalink / raw)
To: linux-kernel, linux-phy, linux-arm-kernel, Alim Akhtar,
linux-scsi
Cc: Martin K . Petersen, pankaj.dubey, krzysztof.kozlowski+dt,
robh+dt, devicetree, chanho61.park, vkoul, avri.altman,
bvanassche
On Fri, 10 Jun 2022 16:11:13 +0530, Alim Akhtar wrote:
> This series adds support for UFS controller found in FSD SoC.
> The HCI is almost same as found on other Exynos SoCs with minor
> differences. This also adds the required UFS-PHY driver changes.
>
> Patch 2/6: common change to handle different CDR offsets
>
> *Changes since v3:
> - Addressed review comments on patch 6/6 from Chanho
>
> [...]
Applied to 5.20/scsi-queue, thanks!
[4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible
https://git.kernel.org/mkp/scsi/c/ea83df8e3bd0
[5/6] ufs: host: ufs-exynos: add mphy apb clock mask
https://git.kernel.org/mkp/scsi/c/daa782a51ec8
[6/6] ufs: host: ufs-exynos: add support for fsd ufs hci
https://git.kernel.org/mkp/scsi/c/216f74e8059a
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^ permalink raw reply [flat|nested] 15+ messages in thread