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Thu, 29 Sep 2022 14:39:37 +0200 Date: Thu, 29 Sep 2022 14:39:36 +0200 From: Johan Hovold To: Dmitry Baryshkov Cc: Johan Hovold , Vinod Koul , Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , Neil Armstrong , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 11/11] phy: qcom-qmp-pcie: drop bogus register update Message-ID: References: <20220929092916.23068-1-johan+linaro@kernel.org> <20220929092916.23068-12-johan+linaro@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220929_053932_550024_002F7A1A X-CRM114-Status: GOOD ( 21.23 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Thu, Sep 29, 2022 at 01:18:05PM +0300, Dmitry Baryshkov wrote: > On Thu, 29 Sept 2022 at 12:29, Johan Hovold wrote: > > > > Since commit 0d58280cf1e6 ("phy: Update PHY power control sequence") the > > PHY is powered on before configuring the registers and only the MSM8996 > > PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS > > initialisation table, may possibly require a second update afterwards. > > > > To make things worse, the POWER_DOWN_CONTROL register lies at a > > different offset on more recent SoCs so that the second update, which > > still used a hard-coded offset, would write to an unrelated register > > (e.g. a revision-id register on SC8280XP). > > > > As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop > > the bogus register update. > > > > Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") added support > > Unless somebody confirms that this write is not needed on 8998 and > sdm845, I'd prefer a two stage fix here: > - changing this to write to proper register (and maybe moving to the > top of patch series, as we'd want to backport this to the last few > kernels) It already is the "proper" register for the v2 platforms that may conceivably need it it. For the rest it is clearly just broken. And I don't think this needs to block the rest of the series. That's why I moved it last. If we decide to backport this we have other context changes in -next to handle anyway. > - dropping the write completely. But sure, doing it in two steps is a possibility. > Meanwhile I'll try testing this patchset on rb3 and checking whether > it makes any difference or not. Thanks for doing that. Johan -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy