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X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Manivannan, [ . . . ] > > > + phys = <&pcie1_phy>; > > > + phy-names = "pciephy"; > > > + > > > + interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>, > > > + <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>; > > > + interconnect-names = "pcie-mem", "cpu-pcie"; > > > > Can you check if the controller supports cache coherency? If so, you need to add > > 'dma-coherent'. > > Ok. Confirmed with h/w person. The controller doesn't support cache coherance. Thanks Varada -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy