From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76531EE49AA for ; Tue, 22 Aug 2023 14:08:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IcN3h51/+xkFI8dObnpjyikCuJJSeoqYHUAO5+TWQgk=; b=MLif4qcB76X2wI FxicOUIbr62uKOcxwX7socHOGyrAqZLWxhMy+lfQ4mC1NO9Vwl8c+7RhXpHArPycej7gzA0UTG1MK EXfRo64PQCVqxjG711SC8Plq5T7YBbku24m6h5Lq9UtjaJxyy5ADE+zGrzj7+VGE96JUHCCqOdSPo OP+cubI1QeElcafioBTI/WRfe8IyfC+N12HDb8d1R6UMiAq0dEywPycI+Daz4scfMQdxcFBAVUfzK 9y3WxMjl16cid2JHzg4rmwAGZuG9zy94v+6c7/arffN2nJ4XiVq+YRDXxFBnc+0BvR22dfSV0H5nR i2C8YMuIpEQQrArLoBzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qYS3q-00GAwD-2a; Tue, 22 Aug 2023 14:08:46 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qYS3m-00GArN-2E for linux-phy@lists.infradead.org; Tue, 22 Aug 2023 14:08:44 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2199D657FF; Tue, 22 Aug 2023 14:08:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A276DC433C7; Tue, 22 Aug 2023 14:08:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692713321; bh=OS10fDwOUMWExZhrVqmCAgd89KllBXNeOlllIehfRsM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=j+MgbxoubPMoMmjyLzQrh0dEVv6SZRr3P531BfUeNwK1q2shmGknZkxuo/Ri+jou6 /iBbX27yJoPhicKGZJqCryzpgn6prSP16RCw6liNPngbt1rt0ceL0VzmvNybCwF0KV LJE+OTiUTcmJFhsTRjLtUkgmUJ/IROE4kUWW9UHePBK6AXnbgFO62quqvpCgzNedhX A86iyDzj7sVqLraBpcn/FOFmGNxVEuI+k18O66dKiH2TzFaF5ChLGlbVIb/ToP2XUK kqb/UI2uS1lJkUe6nVwXaxnMd4DVghbQlF+CSueRAQ49yq9T9kxLg+YzBVEC/0CP1w fS9Wenkp7n0xA== Date: Tue, 22 Aug 2023 19:38:35 +0530 From: Vinod Koul To: Nitin Rawat Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manish Pandey Subject: Re: [PATCH V2 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280 Message-ID: References: <20230819115223.9479-1-quic_nitirawa@quicinc.com> <20230819115223.9479-3-quic_nitirawa@quicinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230819115223.9479-3-quic_nitirawa@quicinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230822_070842_834223_BF0CDBF8 X-CRM114-Status: GOOD ( 14.75 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 19-08-23, 17:22, Nitin Rawat wrote: > Add SC7280 specific register layout and table configs. > > Co-developed-by: Manish Pandey > Signed-off-by: Manish Pandey > Signed-off-by: Nitin Rawat > --- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++ > 1 file changed, 142 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > index 3927eba8e468..b22198d09508 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > @@ -177,6 +177,111 @@ static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { > QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), > }; > > +static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), > +}; > + > +static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), > +}; > + > +static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = { > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6D), Lower case please (here and few other places) > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0A), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1F), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xFF), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xD8), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xAA), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), > +}; > + > +static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), > +}; > + > static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), > @@ -888,6 +993,40 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { > .regs = ufsphy_v5_regs_layout, > }; > > +static const struct qmp_phy_cfg sc7280_ufsphy_cfg = { sorted alphabetically please > + .lanes = 2, > + > + .offsets = &qmp_ufs_offsets, > + > + .tbls = { > + .serdes = sm8150_ufsphy_serdes, > + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), > + .tx = sc7280_ufsphy_tx, > + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx), > + .rx = sc7280_ufsphy_rx, > + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx), > + .pcs = sc7280_ufsphy_pcs, > + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs), > + }, > + .tbls_hs_b = { > + .serdes = sm8150_ufsphy_hs_b_serdes, > + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), > + }, > + .tbls_hs_g4 = { > + .tx = sm8250_ufsphy_hs_g4_tx, > + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), > + .rx = sc7280_ufsphy_hs_g4_rx, > + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx), > + .pcs = sm8150_ufsphy_hs_g4_pcs, > + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), > + }, > + .clk_list = sm8450_ufs_phy_clk_l, > + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), > + .vreg_list = qmp_phy_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > + .regs = ufsphy_v4_regs_layout, > +}; > + > static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { > .lanes = 2, > > @@ -1648,6 +1787,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { > }, { > .compatible = "qcom,sa8775p-qmp-ufs-phy", > .data = &sa8775p_ufsphy_cfg, > + }, { > + .compatible = "qcom,sc7280-qmp-ufs-phy", > + .data = &sc7280_ufsphy_cfg, > }, { > .compatible = "qcom,sc8180x-qmp-ufs-phy", > .data = &sm8150_ufsphy_cfg, > -- > 2.17.1 -- ~Vinod -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy