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Tue, 30 Apr 2024 06:31:26 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43U6VP4x008281 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 Apr 2024 06:31:25 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 29 Apr 2024 23:31:18 -0700 Date: Tue, 30 Apr 2024 12:01:15 +0530 From: Varadarajan Narayanan To: Dmitry Baryshkov CC: Alex G. , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Michael Turquette , Stephen Boyd , Manivannan Sadhasivam , , , , , , Subject: Re: [PATCH v3 6/7] phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY Message-ID: References: <20240415182052.374494-1-mr.nuke.me@gmail.com> <20240415182052.374494-7-mr.nuke.me@gmail.com> <6726fa2b-f5fe-10fb-6aab-f76d61f0b3cd@gmail.com> <4a7b1e1d-ac68-4857-8925-f90c9e123fd1@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Kz9y3fLxciuZSj0DW7v68K0H1YjdIf0m X-Proofpoint-ORIG-GUID: Kz9y3fLxciuZSj0DW7v68K0H1YjdIf0m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-30_02,2024-04-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 adultscore=0 spamscore=0 mlxscore=0 phishscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404300046 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_233139_416582_6CA36058 X-CRM114-Status: GOOD ( 33.15 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Mon, Apr 29, 2024 at 01:55:32PM +0300, Dmitry Baryshkov wrote: > On Mon, 29 Apr 2024 at 09:20, Varadarajan Narayanan > wrote: > > > > On Wed, Apr 17, 2024 at 12:50:49AM +0300, Dmitry Baryshkov wrote: > > > On Wed, 17 Apr 2024 at 00:25, Alex G. wrote: > > > > > > > > Hi Dmitry, > > > > > > > > On 4/15/24 16:25, mr.nuke.me@gmail.com wrote: > > > > > > > > > > > > > > > On 4/15/24 15:10, Dmitry Baryshkov wrote: > > > > >> On Mon, 15 Apr 2024 at 21:23, Alexandru Gagniuc > > > > >> wrote: > > > > >>> > > > > >>> Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream > > > > >>> 5.4 kernel. Only the serdes and pcs_misc tables are new, the others > > > > >>> being reused from IPQ8074 and IPQ6018 PHYs. > > > > >>> > > > > >>> Signed-off-by: Alexandru Gagniuc > > > > >>> --- > > > > >>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++- > > > > >>> .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++ > > > > >>> 2 files changed, 149 insertions(+), 1 deletion(-) > > > > >>> > > > > >> > > > > >> [skipped] > > > > >> > > > > >>> @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem > > > > >>> *base, u32 offset, u32 val) > > > > >>> > > > > >>> /* list of clocks required by phy */ > > > > >>> static const char * const qmp_pciephy_clk_l[] = { > > > > >>> - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", > > > > >>> + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", > > > > >>> "anoc", "snoc" > > > > >> > > > > >> Are the NoC clocks really necessary to drive the PHY? I think they are > > > > >> usually connected to the controllers, not the PHYs. > > > > > > > > > > The system will hang if these clocks are not enabled. They are also > > > > > attached to the PHY in the QCA 5.4 downstream kernel. > > > > > > Interesting. > > > I see that Varadarajan is converting these clocks into interconnects. > > > Maybe it's better to wait for those patches to land and use > > > interconnects instead. I think it would better suit the > > > infrastructure. > > > > > > Varadarajan, could you please comment, are these interconnects > > > connected to the PHY too or just to the PCIe controller? > > > > Sorry for the late response. Missed this e-mail. > > > > These 2 clks are related to AXI port clk on Aggnoc/SNOC, not > > directly connected to PCIE wrapper, but it should be enabled to > > generate pcie traffic. > > So, are they required for the PHY or are they required for the PCIe > controller only? These 2 clks are required for PCIe controller only. PCIE controller need these clks to send/receive axi pkts. Thanks Varada > > > > They are named "anoc_lane", and "snoc_lane" in the downstream kernel. > > > > Would you like me to use these names instead? > > > > > > I'm fine either way. > > > > > > > -- > With best wishes > Dmitry -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy