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Fri, 26 Jul 2024 16:38:53 +0200 Date: Fri, 26 Jul 2024 16:38:52 +0200 From: Johan Hovold To: Abel Vesa Cc: Vinod Koul , Kishon Vijay Abraham I , Johan Hovold , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Qiang Yu Subject: Re: [PATCH] phy: qcom: qmp-pcie: Configure all tables on port B PHY Message-ID: References: <20240726-phy-qcom-qmp-pcie-write-all-tbls-second-port-v1-1-751b9ee01184@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240726-phy-qcom-qmp-pcie-write-all-tbls-second-port-v1-1-751b9ee01184@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240726_073850_766322_715B2A70 X-CRM114-Status: GOOD ( 16.18 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Fri, Jul 26, 2024 at 11:09:14AM +0300, Abel Vesa wrote: > From: Qiang Yu > > Currently, only the RX and TX tables are written to the second PHY > (port B) when the 4-lanes mode is configured, but according to Qualcomm > internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need > to be written as well. > > Signed-off-by: Qiang Yu > Signed-off-by: Abel Vesa > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > index 5b36cc7ac78b..fd59ebd32f5f 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > @@ -3660,18 +3660,30 @@ static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_ > { > const struct qmp_phy_cfg *cfg = qmp->cfg; > const struct qmp_pcie_offsets *offs = cfg->offsets; > - void __iomem *tx3, *rx3, *tx4, *rx4; > + void __iomem *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd, *serdes; Please order these as serdes, tx/rx, pcs, pcs_misc, ln_shrd so that it matches the order port_a is programmed (even if the hardware doesn't care about this). > > tx3 = qmp->port_b + offs->tx; > rx3 = qmp->port_b + offs->rx; > tx4 = qmp->port_b + offs->tx2; > rx4 = qmp->port_b + offs->rx2; > + serdes = qmp->port_b + offs->serdes; And use the same order here (move serdes above tx3). > + pcs = qmp->port_b + offs->pcs; > + pcs_misc = qmp->port_b + offs->pcs_misc; > + ln_shrd = qmp->port_b + offs->ln_shrd; > qmp_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); > qmp_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); > > qmp_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); > qmp_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); > + > + qmp_configure(serdes, tbls->serdes, tbls->serdes_num); > + qmp_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); And here (e.g. move serdes above tx3). > + > + qmp_configure(pcs, tbls->pcs, tbls->pcs_num); > + qmp_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); > + > + qmp_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); > } Johan -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy