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From: Johan Hovold <johan@kernel.org>
To: Qiang Yu <quic_qianyu@quicinc.com>
Cc: manivannan.sadhasivam@linaro.org, vkoul@kernel.org,
	kishon@kernel.org, robh@kernel.org, andersson@kernel.org,
	konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org,
	quic_msarkar@quicinc.com, quic_devipriy@quicinc.com,
	dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org,
	neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org,
	linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH v4 6/6] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100
Date: Tue, 24 Sep 2024 16:43:33 +0200	[thread overview]
Message-ID: <ZvLQFSjwR-TvHbm_@hovoldconsulting.com> (raw)
In-Reply-To: <20240924101444.3933828-7-quic_qianyu@quicinc.com>

On Tue, Sep 24, 2024 at 03:14:44AM -0700, Qiang Yu wrote:
> Describe PCIe3 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe3.

> @@ -2907,6 +2907,208 @@ mmss_noc: interconnect@1780000 {
>  			#interconnect-cells = <2>;
>  		};
>  
> +		pcie3: pcie@1bd0000 {
> +			device_type = "pci";
> +			compatible = "qcom,pcie-x1e80100";

> +			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "msi0",
> +					  "msi1",
> +					  "msi2",
> +					  "msi3",
> +					  "msi4",
> +					  "msi5",
> +					  "msi6",
> +					  "msi7",
> +					  "global";

This ninth "global" interrupt is not described by the bindings, which
would also need to be updated. What is it used for?

Johan

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  parent reply	other threads:[~2024-09-24 14:43 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-24 10:14 [PATCH v4 0/6] Add support for PCIe3 on x1e80100 Qiang Yu
2024-09-24 10:14 ` [PATCH v4 1/6] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 Qiang Yu
2024-09-24 10:14 ` [PATCH v4 2/6] dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml Qiang Yu
2024-09-24 14:08   ` Manivannan Sadhasivam
2024-09-24 18:39   ` Krzysztof Kozlowski
2024-09-24 10:14 ` [PATCH v4 3/6] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Qiang Yu
2024-09-24 15:15   ` Johan Hovold
2024-09-25  3:38     ` Qiang Yu
2024-09-25  8:14       ` Johan Hovold
2024-09-24 10:14 ` [PATCH v4 4/6] clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks Qiang Yu
2024-09-24 14:31   ` Johan Hovold
2024-09-25  3:40     ` Qiang Yu
2024-09-24 10:14 ` [PATCH v4 5/6] PCI: qcom: Add support for X1E80100 SoC Qiang Yu
2024-09-24 13:50   ` Manivannan Sadhasivam
2024-09-24 15:17     ` Johan Hovold
2024-09-25  3:47       ` Qiang Yu
2024-09-25  8:07         ` Manivannan Sadhasivam
2024-09-26  3:28           ` Qiang Yu
2024-09-26  5:19             ` Qiang Yu
2024-09-30  7:25               ` Manivannan Sadhasivam
2024-09-25  3:44     ` Qiang Yu
2024-09-24 10:14 ` [PATCH v4 6/6] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Qiang Yu
2024-09-24 14:06   ` Manivannan Sadhasivam
2024-09-24 14:26   ` Konrad Dybcio
2024-09-25  3:57     ` Qiang Yu
2024-09-25  8:05     ` Manivannan Sadhasivam
2024-09-25  9:30       ` Konrad Dybcio
2024-09-25  9:46         ` Konrad Dybcio
2024-09-25 12:52           ` Manivannan Sadhasivam
2024-09-26  3:15             ` Qiang Yu
2024-09-30  7:32               ` Manivannan Sadhasivam
2024-09-24 14:43   ` Johan Hovold [this message]
2024-09-25  6:37     ` Qiang Yu
2024-09-25  7:58       ` Manivannan Sadhasivam

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