From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 485A6C369AA for ; Wed, 25 Sep 2024 08:14:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eWB5YS70onWwEy0jtnSxRdZSkMQHc89kx8Zy+BZABTQ=; b=c1m1xfStIKfsL3 ef6bI2v+Wj8r9vahihpdamHrgpeYcCl4fWQ/uYMR70flhVXcajVOVl2yT8HFgf+4lDLjz5KNwFGOF AehzKPGVGM6BOovBGa+IA376EohGQFQBc6cqBMmkFVENKs634ceBMPo0BkEzVMqxbGFKDI7xAExUd FGJ77lA+P2vilgo2QBM848GpGVvGOAc8u5EcrqN6daHyV9wmrXD8Vu8pDAdvjshFc93xlKd7aCcs2 6Eik/PdrESqDEEQHE/a2+f2nstB6lECmYAHTxSZ9nlOa5s6wiD7y+R14lbRwYK9cF4KqtZ7lzMM3X Tejw/MzIbGwUr0R3++DA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1stNAg-00000004TYv-447Q; Wed, 25 Sep 2024 08:14:50 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1stNAe-00000004TYa-1uxy for linux-phy@lists.infradead.org; Wed, 25 Sep 2024 08:14:49 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id C08745C5C44; Wed, 25 Sep 2024 08:14:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 582D6C4CEC3; Wed, 25 Sep 2024 08:14:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727252087; bh=FgyJaMf+udJs61Oebn2XB8BHj/lhCR104SBb9JsLSw4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=AcA53YsvfCo9m8w9ji1QV5Lmm/Lc2HRphqg6nANVhqdPaXhQiPRvtW3/dPWgkJJMz pSwsRBsnUVNZa1WJAipdt4wOvzp9Q7kDQBZFEv4V2Vhixj+7JFciU/hwLsHyR78r/a hxmjzst/RVjP4yxB9m8XlfR8SOoEDMVXWh1P30zY5byXK9Ne2QfaL0SslZHH8VRMKc wRcDSIzFzBorneBLhpufk5PoMg8GDM2h2v/StzE/rRaEwJUvGsyGtIi2kQ+e3Ak5Eh FCP4P1pwZJElGNlDGVCYkxumj2DQgMmOcYWyORnqRkxiinZlJFy08rtk2USCXlYw3O KawhRLRM0g8Xw== Received: from johan by theta with local (Exim 4.98) (envelope-from ) id 1stNAZ-000000000c9-3ZrB; Wed, 25 Sep 2024 10:14:43 +0200 Date: Wed, 25 Sep 2024 10:14:43 +0200 From: Johan Hovold To: Qiang Yu Cc: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 3/6] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Message-ID: References: <20240924101444.3933828-1-quic_qianyu@quicinc.com> <20240924101444.3933828-4-quic_qianyu@quicinc.com> <3d4a8243-5c2f-41c4-85ce-6e072331f4f3@quicinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3d4a8243-5c2f-41c4-85ce-6e072331f4f3@quicinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240925_011448_568105_12827475 X-CRM114-Status: GOOD ( 17.24 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Wed, Sep 25, 2024 at 11:38:46AM +0800, Qiang Yu wrote: > > On 9/24/2024 11:15 PM, Johan Hovold wrote: > > On Tue, Sep 24, 2024 at 03:14:41AM -0700, Qiang Yu wrote: > > > Currently driver supports only x4 lane based functionality using tx/rx and > > > tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3, > > > PCIe3 related QMP PHY provides additional programming which are available > > > as txz and rxz based register set. Hence adds txz and rxz based registers > > > usage and programming sequences. > > > Phy register setting for txz and rxz will > > > be applied to all 8 lanes. Some lanes may have different settings on > > > several registers than txz/rxz, these registers should be programmed after > > > txz/rxz programming sequences completing. > > Please expand and clarify what you mean by this. > PCIe3 supports 8 lanes, so in general, we have to program 8 pairs tx/rx > registers. However, most of tx/rx registers of different lanes have > same settings, so the configuration for all 8 lanes tx/rx registers is > a little repetitive. > > Hence, txz/rxz registers are included. The values programmed into txz/rxz > registers by software will be "broadcasted" to all 8 lanes by hardware. > Some lanes may have different settings on several registers than txz/rxz. > In order to ensure the different values take effect, they need to be > programmed after txz/rxz programming sequences completing. Thanks for clarifying. This is how I interpreted it, but please include (some or all of of) what you just wrote to make this more clear in the commit message. Johan -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy