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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Tue, Nov 12, 2024 at 03:05:57PM +0530, Krishna Kurapati wrote: > > > On 11/12/2024 2:43 PM, Varadarajan Narayanan wrote: > > The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0 > > can connect to either of USB2.0 or USB3.0 phy and operate in the > > respective mode. > > > > Signed-off-by: Varadarajan Narayanan > > --- > > arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 67 +++++++++ > > arch/arm64/boot/dts/qcom/ipq5424.dtsi | 153 ++++++++++++++++++++ > > 2 files changed, 220 insertions(+) > > > > [...] > > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > > index 5e219f900412..d8c045a311c2 100644 > > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi > > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > > @@ -233,6 +233,159 @@ intc: interrupt-controller@f200000 { > > msi-controller; > > }; > > + qusb_phy_1: phy@71000 { > > + compatible = "qcom,ipq5424-qusb2-phy"; > > + reg = <0 0x00071000 0 0x180>; > > + #phy-cells = <0>; > > + > > + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > > + <&xo_board>; > > + clock-names = "cfg_ahb", "ref"; > > + > > + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; > > + status = "disabled"; > > + }; > > + > > + usb2: usb2@1e00000 { > > + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; > > + reg = <0 0x01ef8800 0 0x400>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + clocks = <&gcc GCC_USB1_MASTER_CLK>, > > + <&gcc GCC_USB1_SLEEP_CLK>, > > + <&gcc GCC_USB1_MOCK_UTMI_CLK>, > > + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > > + <&gcc GCC_CNOC_USB_CLK>; > > + > > + clock-names = "core", > > + "sleep", > > + "mock_utmi", > > + "iface", > > + "cfg_noc"; > > + > > + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, > > + <&gcc GCC_USB1_MOCK_UTMI_CLK>; > > + assigned-clock-rates = <200000000>, > > + <24000000>; > + > > Shouldn't this be 19.2MHz ? XO is 24MHz in this SoC. > > + interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, > > + <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, > > + <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, > > + <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "pwr_event", > > + "qusb2_phy", > > + "dm_hs_phy_irq", > > + "dp_hs_phy_irq"; > > + > > Please check the hs_phy_irq as well and add it if its present. Will add. > > + resets = <&gcc GCC_USB1_BCR>; > > + qcom,select-utmi-as-pipe-clk; > > + status = "disabled"; > > + > > + dwc_1: usb@1e00000 { > > + compatible = "snps,dwc3"; > > + reg = <0 0x01e00000 0 0xe000>; > > + clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>; > > + clock-names = "ref"; > > Another clock in dwc3 node ? > > > + interrupts = ; > > + phys = <&qusb_phy_1>; > > + phy-names = "usb2-phy"; > > + tx-fifo-resize; > > + snps,is-utmi-l1-suspend; > > + snps,hird-threshold = /bits/ 8 <0x0>; > > + snps,dis_u2_susphy_quirk; > > + snps,dis_u3_susphy_quirk; > > + }; > > + }; > > + > > + qusb_phy_0: phy@7b000 { > > + compatible = "qcom,ipq5424-qusb2-phy"; > > + reg = <0 0x0007b000 0 0x180>; > > + #phy-cells = <0>; > > + > > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > + <&xo_board>; > > + clock-names = "cfg_ahb", "ref"; > > + > > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > > + status = "disabled"; > > + }; > > + > > + ssphy_0: phy@7d000 { > > + compatible = "qcom,ipq5424-qmp-usb3-phy"; > > + reg = <0 0x0007d000 0 0xa00>; > > + #phy-cells = <0>; > > + > > + clocks = <&gcc GCC_USB0_AUX_CLK>, > > + <&xo_board>, > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > + <&gcc GCC_USB0_PIPE_CLK>; > > + clock-names = "aux", > > + "ref", > > + "cfg_ahb", > > + "pipe"; > > + > > + resets = <&gcc GCC_USB0_PHY_BCR>, > > + <&gcc GCC_USB3PHY_0_PHY_BCR>; > > + reset-names = "phy", > > + "phy_phy"; > > + > > + #clock-cells = <0>; > > + clock-output-names = "usb0_pipe_clk"; > > + > > + status = "disabled"; > > + }; > > + > > + usb3: usb3@8a00000 { > > + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; > > + reg = <0 0x08af8800 0 0x400>; > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + clocks = <&gcc GCC_USB0_MASTER_CLK>, > > + <&gcc GCC_USB0_SLEEP_CLK>, > > + <&gcc GCC_USB0_MOCK_UTMI_CLK>, > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > + <&gcc GCC_CNOC_USB_CLK>; > > + > > + clock-names = "core", > > + "sleep", > > + "mock_utmi", > > + "iface", > > + "cfg_noc"; > > + > > + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, > > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > > + assigned-clock-rates = <200000000>, > > + <24000000>; > > + > > same comment as above, isn't this supposed to be 19.2MHz ? XO is 24MHz in this SoC. > > + interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, > > + <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "pwr_event", > > + "qusb2_phy"; > > + > > DP/ DM interrupts ? Will add. > > + resets = <&gcc GCC_USB_BCR>; > > + status = "disabled"; > > + > > + dwc_0: usb@8a00000 { > > + compatible = "snps,dwc3"; > > + reg = <0 0x08a00000 0 0xcd00>; > > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > > + clock-names = "ref"; > > + interrupts = ; > > + phys = <&qusb_phy_0>, <&ssphy_0>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + tx-fifo-resize; > > + snps,is-utmi-l1-suspend; > > + snps,hird-threshold = /bits/ 8 <0x0>; > > + snps,dis_u2_susphy_quirk; > > + snps,dis_u3_susphy_quirk; > > Disable u1/u2 entry as well please. Will add. Thanks Varada -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy