From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: George Moussalem <george.moussalem@outlook.com>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux-phy@lists.infradead.org,
andersson@kernel.org, bhelgaas@google.com, conor+dt@kernel.org,
devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org,
kishon@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org,
kw@linux.com, lpieralisi@kernel.org,
manivannan.sadhasivam@linaro.org, p.zabel@pengutronix.de,
quic_nsekar@quicinc.com, robh@kernel.org, robimarko@gmail.com,
vkoul@kernel.org
Cc: quic_srichara@quicinc.com
Subject: Re: [PATCH v3 3/6] dt-bindings: PCI: qcom: Add IPQ5018 SoC
Date: Wed, 5 Mar 2025 16:51:01 +0100 [thread overview]
Message-ID: <a95b4c01-9d8c-49eb-8242-93ae411caec0@linaro.org> (raw)
In-Reply-To: <DS7PR19MB8883E7167E44F92DBC29FF3C9DCB2@DS7PR19MB8883.namprd19.prod.outlook.com>
On 05/03/2025 14:41, George Moussalem wrote:
> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>
> From: Nitheesh Sekar <quic_nsekar@quicinc.com>
Nope, that's not a correct chain. Apply it yourself and check results.
>
> Add support for the PCIe controller on the Qualcomm
> IPQ5108 SoC to the bindings.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Also not really correct. I did not provide tag to Nitheesh patch. How
the tag was added there? b4?
> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 49 +++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
...
> + reset-names:
> + items:
> + - const: pipe # PIPE reset
> + - const: sleep # Sleep reset
> + - const: sticky # Core sticky reset
> + - const: axi_m # AXI master reset
> + - const: axi_s # AXI slave reset
> + - const: ahb # AHB reset
> + - const: axi_m_sticky # AXI master sticky reset
> + - const: axi_s_sticky # AXI slave sticky reset
> + interrupts:
> + minItems: 8
> + interrupt-names:
> + minItems: 8
Why is this flexible?
> + items:
> + - const: msi0
> + - const: msi1
> + - const: msi2
> + - const: msi3
> + - const: msi4
> + - const: msi5
> + - const: msi6
> + - const: msi7
> + - const: global
> +
Best regards,
Krzysztof
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next prev parent reply other threads:[~2025-03-05 15:51 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250305134239.2236590-1-george.moussalem@outlook.com>
2025-03-05 13:41 ` [PATCH v3 0/6] Enable IPQ5018 PCI support George Moussalem
2025-03-05 16:49 ` Krzysztof Kozlowski
2025-03-05 16:59 ` George Moussalem
2025-03-06 7:18 ` Krzysztof Kozlowski
2025-03-05 13:41 ` [PATCH v3 1/6] dt-bindings: phy: qcom: uniphy-pcie: Add ipq5018 compatible George Moussalem
2025-03-05 13:41 ` [PATCH v3 2/6] phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018 George Moussalem
2025-03-05 20:39 ` Dmitry Baryshkov
2025-03-08 14:25 ` Konrad Dybcio
2025-03-08 15:29 ` Dmitry Baryshkov
2025-03-05 13:41 ` [PATCH v3 3/6] dt-bindings: PCI: qcom: Add IPQ5018 SoC George Moussalem
2025-03-05 15:51 ` Krzysztof Kozlowski [this message]
2025-03-05 16:41 ` George Moussalem
2025-03-05 16:45 ` Krzysztof Kozlowski
2025-03-06 7:24 ` Krzysztof Kozlowski
2025-03-13 5:55 ` George Moussalem
2025-03-05 13:41 ` [PATCH v3 4/6] PCI: qcom: Add support for IPQ5018 George Moussalem
2025-03-13 6:00 ` Manivannan Sadhasivam
2025-03-05 13:41 ` [PATCH v3 5/6] arm64: dts: qcom: ipq5018: Add PCIe related nodes George Moussalem
2025-03-08 15:08 ` Konrad Dybcio
2025-03-13 6:09 ` George Moussalem
2025-03-18 7:17 ` Manivannan Sadhasivam
2025-03-18 9:41 ` George Moussalem
2025-03-24 7:33 ` Manivannan Sadhasivam
2025-03-05 13:41 ` [PATCH v3 6/6] arm64: dts: qcom: ipq5018: Enable PCIe George Moussalem
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