From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-rockchip@lists.infradead.org,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RESEND RFC PATCH v4 1/5] PCI: rockchip: Use standard PCIe defines
Date: Fri, 13 Jun 2025 18:01:34 -0300 [thread overview]
Message-ID: <aEyRrtMZ0LidhyOR@geday> (raw)
In-Reply-To: <20250613205023.GA975137@bhelgaas>
On Fri, Jun 13, 2025 at 03:50:23PM -0500, Bjorn Helgaas wrote:
> I don't have access to any of these TRMs, so I only know what's in the
> driver.
>
They are not under NDA and can be obtained though Rockchip's
official site:
https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
> When you say "without fear", are you saying there's a way to do that
> 32-bit write such that the LNKSTA bits are discarded by the hardware?
> Or just that the hardware forces us to accept this potential status
> register corruption?
I meant to say those registers themselves are defined in TRM as 32 bits.
>
> Is this something that could be written using the config access path?
> I guess probably not, based on this:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip-host.c?id=v6.15#n141
>
That certainly looks frightening.
> Bjorn
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next prev parent reply other threads:[~2025-06-13 21:02 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 15:05 [RESEND RFC PATCH v4 0/5] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-13 15:05 ` [RESEND RFC PATCH v4 1/5] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-06-13 20:14 ` Bjorn Helgaas
2025-06-13 20:26 ` Geraldo Nascimento
2025-06-13 20:50 ` Bjorn Helgaas
2025-06-13 21:01 ` Geraldo Nascimento [this message]
2025-06-14 2:31 ` Geraldo Nascimento
2025-06-14 1:38 ` Geraldo Nascimento
2025-06-13 15:05 ` [RESEND RFC PATCH v4 2/5] PCI: rockchip: Drop unused custom registers and bitfields Geraldo Nascimento
2025-06-13 15:06 ` [RESEND RFC PATCH v4 3/5] PCI: rockchip: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-13 20:15 ` Bjorn Helgaas
2025-06-13 20:27 ` Geraldo Nascimento
2025-06-13 15:06 ` [RESEND RFC PATCH v4 4/5] phy: rockchip-pcie: Enable all four lanes Geraldo Nascimento
2025-06-13 15:06 ` [RESEND RFC PATCH v4 5/5] phy: rockchip-pcie: Adjust read mask and write Geraldo Nascimento
2025-06-13 20:20 ` Bjorn Helgaas
2025-06-13 20:32 ` Geraldo Nascimento
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