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From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-rockchip@lists.infradead.org,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Valmantas Paliksa" <walmis@gmail.com>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [RESEND PATCH v9 1/4] PCI: rockchip: Use standard PCIe defines
Date: Mon, 7 Jul 2025 20:04:45 -0300	[thread overview]
Message-ID: <aGxSjb17kz2--_Sf@geday> (raw)
In-Reply-To: <20250707222210.GA2114615@bhelgaas>

On Mon, Jul 07, 2025 at 05:22:10PM -0500, Bjorn Helgaas wrote:
> On Mon, Jun 30, 2025 at 07:24:41PM -0300, Geraldo Nascimento wrote:
> > Current code uses custom-defined register offsets and bitfields for
> > standard PCIe registers. Change to using standard PCIe defines. Since
> > we are now using standard PCIe defines, drop unused custom-defined ones,
> > which are now referenced from offset at added Capabilities Register.
> 
> > @@ -278,10 +278,10 @@ static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
> >  		power = power / 10;
> >  	}
> >  
> > -	status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
> > -	status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
> > -		  (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
> > -	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
> > +	status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP);
> > +	status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power);
> > +	status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_SCL, scale);
> 
> Added #include <linux/bitfield.h> for this:
> 
>   CC      drivers/pci/controller/pcie-rockchip-host.o
> drivers/pci/controller/pcie-rockchip-host.c: In function ‘rockchip_pcie_set_power_limit’:
> drivers/pci/controller/pcie-rockchip-host.c:272:24: error: implicit declaration of function ‘FIELD_MAX’ [-Werror=implicit-function-declaration]
>   272 |         while (power > FIELD_MAX(PCI_EXP_DEVCAP_PWR_VAL)) {
>       |                        ^~~~~~~~~
> drivers/pci/controller/pcie-rockchip-host.c:282:19: error: implicit declaration of function ‘FIELD_PREP’ [-Werror=implicit-function-declaration]
>   282 |         status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power);
>       |                   ^~~~~~~~~~
>

Hi Bjorn,

Ugh, what a miss! Thank you for taking care of this!

Geraldo Nascimento

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  reply	other threads:[~2025-07-07 23:05 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-30 22:24 [RESEND PATCH v9 0/4] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-30 22:24 ` [RESEND PATCH v9 1/4] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-07-01  7:54   ` Philipp Stanner
2025-07-01 12:03     ` Geraldo Nascimento
2025-07-01 12:44       ` Manivannan Sadhasivam
2025-07-07 22:22   ` Bjorn Helgaas
2025-07-07 23:04     ` Geraldo Nascimento [this message]
2025-06-30 22:24 ` [RESEND PATCH v9 2/4] PCI: rockchip: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-30 22:25 ` [RESEND PATCH v9 3/4] phy: rockchip-pcie: Enable all four lanes if required Geraldo Nascimento
2025-06-30 22:25 ` [RESEND PATCH v9 4/4] phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal Geraldo Nascimento
2025-07-01  7:43 ` (subset) [RESEND PATCH v9 0/4] PCI: rockchip: Improve driver quality Manivannan Sadhasivam
2025-07-22 13:37 ` Vinod Koul

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