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From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: linux-rockchip@lists.infradead.org,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 3/4] phy: rockchip-pcie: Enable all four lanes if required
Date: Mon, 21 Jul 2025 11:52:12 -0300	[thread overview]
Message-ID: <aH5UHPAtAVb2snSK@geday> (raw)
In-Reply-To: <2affed16-f3c4-47d3-9ca6-e4f48e875367@arm.com>

On Mon, Jun 30, 2025 at 02:48:25PM +0100, Robin Murphy wrote:
> On 29/06/2025 9:58 pm, Geraldo Nascimento wrote:
> > Current code enables only Lane 0 because pwr_cnt will be incremented on
> > first call to the function. Let's reorder the enablement code to enable
> > all 4 lanes through GRF.
> 
> As usual the TRM isn't very clear, but the way it describes the 
> GRF_SOC_CON_5_PCIE bits does suggest they're driving external input 
> signals of the phy block, so it seems reasonable that it could be OK to 
> update the register itself without worrying about releasing the phy from 
> reset first. In that case I'd agree this seems the cleanest fix, and if 
> it works empirically then I think I'm now sufficiently convinced too;
> 
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>

Hi everyone,

Patches 1 and 2 of this series were merged thhrough pci git but patches
3 and 4 of present series got R-b's but were completely ignored by phy
maintainers.

Do you think it's fair if I resend these ones with a new, phy only, cover
letter but keep the R-b tags?

Thank you,
Geraldo Nascimento

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      parent reply	other threads:[~2025-07-21 16:43 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-29 12:47 [PATCH v7 0/4] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-29 12:47 ` [PATCH v7 1/4] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-06-29 12:48 ` [PATCH v7 2/4] PCI: rockchip: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-29 12:48 ` [PATCH v7 4/4] phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal Geraldo Nascimento
2025-06-30  8:49   ` neil.armstrong
2025-06-29 20:58 ` [PATCH v7 3/4] phy: rockchip-pcie: Enable all four lanes if required Geraldo Nascimento
2025-06-30  8:49   ` neil.armstrong
2025-06-30 13:48   ` Robin Murphy
2025-06-30 17:55     ` Geraldo Nascimento
2025-07-21 14:52     ` Geraldo Nascimento [this message]

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