[PATCH 0/5] Add USB support for Canaan K230

[PATCH 0/5] Add USB support for Canaan K230

[Jiayu Du]

Add support for the USB PHY and DWC2 IP which is used by Canaan K230,
and made relevant changes to the DTS.

This series is based on the initial 100ask K230 DshanPi series [1] which
is based on the clock and pinctrl series. Check the details in the link.

Link: https://lore.kernel.org/all/20251229061318.16756-1-jiayu.riscv@isrc.iscas.ac.cn/ [1]

Jiayu Du (5):
  dt-bindings: phy: Add Canaan K230 USB2.0 PHY DT schema
  dt-bindings: soc: canaan: Add top syscon for Canaan K230 SoC
  dt-bindings: usb: dwc2: Add support for Canaan K230 SoC
  phy: usb: Add driver for Canaan K230 USB 2.0 PHY
  riscv: dts: canaan: Add syscon and USB nodes for K230

 .../bindings/phy/canaan,k230-usb-phy.yaml     |  36 +++
 .../soc/canaan/canaan,k230-hisys-cfg.yaml     |  68 +++++
 .../devicetree/bindings/usb/dwc2.yaml         |   3 +
 .../boot/dts/canaan/k230-canmv-dshanpi.dts    |  21 ++
 arch/riscv/boot/dts/canaan/k230.dtsi          |  51 ++++
 drivers/phy/Kconfig                           |   1 +
 drivers/phy/Makefile                          |   1 +
 drivers/phy/canaan/Kconfig                    |  14 +
 drivers/phy/canaan/Makefile                   |   2 +
 drivers/phy/canaan/phy-k230-usb.c             | 272 ++++++++++++++++++
 10 files changed, 469 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml
 create mode 100644 drivers/phy/canaan/Kconfig
 create mode 100644 drivers/phy/canaan/Makefile
 create mode 100644 drivers/phy/canaan/phy-k230-usb.c

-- 
2.52.0


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[PATCH 1/5] dt-bindings: phy: Add Canaan K230 USB2.0 PHY DT schema

[Jiayu Du]

k230-usb-phy driver supports USB 2.0 phys integrated in Canaan
K230 SoC. Add YAML schema for its binding.

Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
 .../bindings/phy/canaan,k230-usb-phy.yaml     | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml b/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
new file mode 100644
index 000000000000..f1c9511c873f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/canaan,k230-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Canaan K230 USB2.0 PHY
+
+maintainers:
+  - Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
+
+properties:
+  compatible:
+    const: canaan,k230-usb-phy
+
+  reg:
+    description:
+      Two register regions for USB PHY in HiSysConfig syscon block.
+    items:
+      - description: USB PHY test control reg (pullup/pulldown config)
+      - description: USB PHY core control reg (PLL/transceiver tuning)
+    minItems: 2
+    maxItems: 2
+
+  clocks:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+
+additionalProperties: false
-- 
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[PATCH 2/5] dt-bindings: soc: canaan: Add top syscon for Canaan K230 SoC

[Jiayu Du]

The Canaan K230 SoC top system controller provides register access
to configure related modules. It includes a USB2 PHY and eMMC/SDIO PHY.

Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
 .../soc/canaan/canaan,k230-hisys-cfg.yaml     | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml

diff --git a/Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml b/Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml
new file mode 100644
index 000000000000..77875f2d4f48
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/canaan/canaan,k230-hisys-cfg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Canaan K230 HiSysConfig system controller
+
+maintainers:
+  - Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
+
+description:
+  The Canaan K230 HiSysConfig system controller provides register access to
+  configure high-speed peripherals (e.g. eMMC/SDIO PHY tuning) and USB PHY
+  configuration.
+
+properties:
+  compatible:
+    items:
+      - const: canaan,k230-hisys-cfg
+      - const: syscon
+      - const: simple-mfd
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  usb-phy@70:
+    $ref: schemas/phy/canaan,k230-usb-phy.yaml#
+    unevaluatedProperties: false
+
+  usb-phy@90:
+    $ref: schemas/phy/canaan,k230-usb-phy.yaml#
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    hi_sys_config: syscon@91585000 {
+        compatible = "canaan,k230-hisys-cfg", "syscon", "simple-mfd";
+        reg = <0x91585000 0x400>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        usbphy0: usb-phy@70 {
+            compatible = "canaan,k230-usb-phy";
+            reg = <0x70 0x1C>, <0xb0 0x8>;
+            clocks = <&sysclk K230_HS_USB0_AHB_GATE>;
+            #phy-cells = <0>;
+        };
+
+        usbphy1: usb-phy@90 {
+            compatible = "canaan,k230-usb-phy";
+            reg = <0x90 0x1C>, <0xb8 0x8>;
+            clocks = <&sysclk K230_HS_USB1_AHB_GATE>;
+            #phy-cells = <0>;
+        };
+    };
-- 
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[PATCH 3/5] dt-bindings: usb: dwc2: Add support for Canaan K230 SoC

[Jiayu Du]

Add 'canaan,k230-usb' compatible string with 'snps,dwc2' as fallback
for the DWC2 IP which is used by Canaan K230.

Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
 Documentation/devicetree/bindings/usb/dwc2.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 6c3a10991b8b..352487c6392a 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -17,6 +17,9 @@ properties:
   compatible:
     oneOf:
       - const: brcm,bcm2835-usb
+      - items:
+          - const: canaan,k230-usb
+          - const: snps,dwc2
       - const: hisilicon,hi6220-usb
       - const: ingenic,jz4775-otg
       - const: ingenic,jz4780-otg
-- 
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[PATCH 4/5] phy: usb: Add driver for Canaan K230 USB 2.0 PHY

[Jiayu Du]

Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
initialization, power management and USB mode switching.

Add Kconfig/Makefile under drivers/phy/canaan/.

Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
 drivers/phy/Kconfig               |   1 +
 drivers/phy/Makefile              |   1 +
 drivers/phy/canaan/Kconfig        |  14 ++
 drivers/phy/canaan/Makefile       |   2 +
 drivers/phy/canaan/phy-k230-usb.c | 272 ++++++++++++++++++++++++++++++
 5 files changed, 290 insertions(+)
 create mode 100644 drivers/phy/canaan/Kconfig
 create mode 100644 drivers/phy/canaan/Makefile
 create mode 100644 drivers/phy/canaan/phy-k230-usb.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0a..95e630749350 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
 source "drivers/phy/cadence/Kconfig"
+source "drivers/phy/canaan/Kconfig"
 source "drivers/phy/freescale/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/ingenic/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494..f07c68f2e283 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,6 +17,7 @@ obj-y					+= allwinner/	\
 					   amlogic/	\
 					   broadcom/	\
 					   cadence/	\
+					   canaan/	\
 					   freescale/	\
 					   hisilicon/	\
 					   ingenic/	\
diff --git a/drivers/phy/canaan/Kconfig b/drivers/phy/canaan/Kconfig
new file mode 100644
index 000000000000..1ff8831846d5
--- /dev/null
+++ b/drivers/phy/canaan/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for Canaan platforms
+#
+config PHY_CANAAN_USB
+	tristate "Canaan USB2 PHY Driver"
+	depends on (ARCH_CANAAN || COMPILE_TEST) && OF
+	select GENERIC_PHY
+	help
+	Enable this driver to support the USB 2.0 PHY controller
+	on Canaan K230 RISC-V SoCs. This PHY controller
+	provides physical layer functionality for USB 2.0 devices.
+	If you have a Canaan K230 board and need USB 2.0 support,
+	say Y or M here.
diff --git a/drivers/phy/canaan/Makefile b/drivers/phy/canaan/Makefile
new file mode 100644
index 000000000000..d73857ba284e
--- /dev/null
+++ b/drivers/phy/canaan/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PHY_CANAAN_USB)		+= phy-k230-usb.o
diff --git a/drivers/phy/canaan/phy-k230-usb.c b/drivers/phy/canaan/phy-k230-usb.c
new file mode 100644
index 000000000000..668618fb2188
--- /dev/null
+++ b/drivers/phy/canaan/phy-k230-usb.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Canaan usb PHY driver
+ *
+ * Copyright (C) 2025 Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define TEST_CTL3_OFFSET	0x0C
+#define CTL0_OFFSET		0x00
+#define CTL1_OFFSET		0x04
+#define USB_IDPULLUP0		BIT(4)
+#define USB_DMPULLDOWN0		BIT(8)
+#define USB_DPPULLDOWN0		BIT(9)
+
+/* USB control register 0 in HiSysConfig system controller */
+/* PLL Integral Path Tune */
+#define USB_CTL0_PLLITUNE_MASK		GENMASK(23, 22)
+
+/* PLL Proportional Path Tune */
+#define USB_CTL0_PLLPTUNE_MASK		GENMASK(21, 18)
+
+/* PLL Bandwidth Adjustment */
+#define USB_CTL0_PLLBTUNE_MASK		GENMASK(17, 17)
+
+/* VReg18 Bypass Control */
+#define USB_CTL0_VREGBYPASS_MASK	GENMASK(16, 16)
+
+/* Retention Mode Enable */
+#define USB_CTL0_RETENABLEN_MASK	GENMASK(15, 15)
+
+/* Reserved Request Input */
+#define USB_CTL0_RESREQIN_MASK		GENMASK(14, 14)
+
+/* External VBUS Valid Select */
+#define USB_CTL0_VBUSVLDEXTSEL0_MASK	GENMASK(13, 13)
+
+/* OTG Block Disable Control */
+#define USB_CTL0_OTGDISABLE0_MASK	GENMASK(12, 12)
+
+/* Drive VBUS Enable */
+#define USB_CTL0_DRVVBUS0_MASK		GENMASK(11, 11)
+
+/* Autoresume Mode Enable */
+#define USB_CTL0_AUTORSMENB0_MASK	GENMASK(10, 10)
+
+/* HS Transceiver Asynchronous Control */
+#define USB_CTL0_HSXCVREXTCTL0_MASK	GENMASK(9, 9)
+
+/* USB 1.1 Transmit Data */
+#define USB_CTL0_FSDATAEXT0_MASK	GENMASK(8, 8)
+
+/* USB 1.1 SE0 Generation */
+#define USB_CTL0_FSSE0EXT0_MASK		GENMASK(7, 7)
+
+/* USB 1.1 Data Enable */
+#define USB_CTL0_TXENABLEN0_MASK	GENMASK(6, 6)
+
+/* Disconnect Threshold */
+#define USB_CTL0_COMPDISTUNE0_MASK	GENMASK(5, 3)
+
+/* Squelch Threshold */
+#define USB_CTL0_SQRXTUNE0_MASK		GENMASK(2, 0)
+
+/* USB control register 1 in HiSysConfig system controller */
+/* Data Detect Voltage */
+#define USB_CTL1_VDATREFTUNE0_MASK	GENMASK(23, 22)
+
+/* VBUS Valid Threshold */
+#define USB_CTL1_OTGTUNE0_MASK		GENMASK(21, 19)
+
+/* Transmitter High-Speed Crossover */
+#define USB_CTL1_TXHSXVTUNE0_MASK	GENMASK(18, 17)
+
+/* FS/LS Source Impedance */
+#define USB_CTL1_TXFSLSTUNE0_MASK	GENMASK(16, 13)
+
+/* HS DC Voltage Level */
+#define USB_CTL1_TXVREFTUNE0_MASK	GENMASK(12, 9)
+
+/* HS Transmitter Rise/Fall Time */
+#define USB_CTL1_TXRISETUNE0_MASK	GENMASK(8, 7)
+
+/* USB Source Impedance */
+#define USB_CTL1_TXRESTUNE0_MASK	GENMASK(6, 5)
+
+/* HS Transmitter Pre-Emphasis Current Control */
+#define USB_CTL1_TXPREEMPAMPTUNE0_MASK	GENMASK(4, 3)
+
+/* HS Transmitter Pre-Emphasis Duration Control */
+#define USB_CTL1_TXPREEMPPULSETUNE0_MASK	GENMASK(2, 2)
+
+/* charging detection */
+#define USB_CTL1_CHRGSRCPUENB0_MASK	GENMASK(1, 0)
+
+#define K230_PHY_CTL0_VAL \
+( \
+	FIELD_PREP(USB_CTL0_PLLITUNE_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL0_PLLPTUNE_MASK, 0xC) | \
+	FIELD_PREP(USB_CTL0_PLLBTUNE_MASK, 0x1) | \
+	FIELD_PREP(USB_CTL0_VREGBYPASS_MASK, 0x1) | \
+	FIELD_PREP(USB_CTL0_RETENABLEN_MASK, 0x1) | \
+	FIELD_PREP(USB_CTL0_RESREQIN_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL0_VBUSVLDEXTSEL0_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL0_OTGDISABLE0_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL0_DRVVBUS0_MASK, 0x1) | \
+	FIELD_PREP(USB_CTL0_AUTORSMENB0_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL0_HSXCVREXTCTL0_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL0_FSDATAEXT0_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL0_FSSE0EXT0_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL0_TXENABLEN0_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL0_COMPDISTUNE0_MASK, 0x3) | \
+	FIELD_PREP(USB_CTL0_SQRXTUNE0_MASK, 0x3) \
+)
+
+#define K230_PHY_CTL1_VAL \
+( \
+	FIELD_PREP(USB_CTL1_VDATREFTUNE0_MASK, 0x1) | \
+	FIELD_PREP(USB_CTL1_OTGTUNE0_MASK, 0x3) | \
+	FIELD_PREP(USB_CTL1_TXHSXVTUNE0_MASK, 0x3) | \
+	FIELD_PREP(USB_CTL1_TXFSLSTUNE0_MASK, 0x3) | \
+	FIELD_PREP(USB_CTL1_TXVREFTUNE0_MASK, 0x3) | \
+	FIELD_PREP(USB_CTL1_TXRISETUNE0_MASK, 0x1) | \
+	FIELD_PREP(USB_CTL1_TXRESTUNE0_MASK, 0x1) | \
+	FIELD_PREP(USB_CTL1_TXPREEMPAMPTUNE0_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL1_TXPREEMPPULSETUNE0_MASK, 0x0) | \
+	FIELD_PREP(USB_CTL1_CHRGSRCPUENB0_MASK, 0x0) \
+)
+
+struct k230_usb_phy {
+	struct regmap *regmap;
+	u32 reg_ctl_offset;
+	u32 reg_test_offset;
+	struct clk *clk;
+};
+
+static int k230_usb_phy_power_on(struct phy *_phy)
+{
+	struct k230_usb_phy *phy = phy_get_drvdata(_phy);
+	int ret;
+	u32 val;
+
+	ret = clk_prepare_enable(phy->clk);
+	if (ret)
+		return ret;
+
+	ret = regmap_write(phy->regmap, phy->reg_ctl_offset + CTL0_OFFSET,
+			   K230_PHY_CTL0_VAL);
+	if (ret)
+		goto err_disable_clk;
+
+	ret = regmap_write(phy->regmap, phy->reg_ctl_offset + CTL1_OFFSET,
+			   K230_PHY_CTL1_VAL);
+	if (ret)
+		goto err_disable_clk;
+
+	val |= USB_IDPULLUP0 | USB_DMPULLDOWN0 | USB_DPPULLDOWN0;
+
+	ret = regmap_update_bits(phy->regmap, phy->reg_test_offset +
+				 TEST_CTL3_OFFSET, val, val);
+	if (ret)
+		goto err_disable_clk;
+
+	return 0;
+
+err_disable_clk:
+	clk_disable_unprepare(phy->clk);
+	return ret;
+}
+
+static int k230_usb_phy_power_off(struct phy *_phy)
+{
+	struct k230_usb_phy *phy = phy_get_drvdata(_phy);
+	int ret;
+	u32 val;
+
+	val = USB_DMPULLDOWN0 | USB_DPPULLDOWN0;
+
+	ret = regmap_update_bits(phy->regmap, phy->reg_test_offset +
+				 TEST_CTL3_OFFSET, val, 0);
+	if (ret)
+		return ret;
+
+	clk_disable_unprepare(phy->clk);
+
+	return 0;
+}
+
+static const struct phy_ops k230_usb_phy_ops = {
+	.power_on = k230_usb_phy_power_on,
+	.power_off = k230_usb_phy_power_off,
+	.owner = THIS_MODULE,
+};
+
+static int k230_usb_phy_probe(struct platform_device *pdev)
+{
+	int ret;
+	u32 offset;
+	struct regmap *regmap;
+	struct phy *generic_phy;
+	struct k230_usb_phy *phy;
+	struct phy_provider *provider;
+	struct device *dev = &pdev->dev;
+
+	regmap = syscon_node_to_regmap(dev->parent->of_node);
+	if (IS_ERR(regmap))
+		return dev_err_probe(dev, PTR_ERR(regmap),
+				     "failed to get syscon regmap\n");
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	phy->regmap = regmap;
+
+
+	ret = of_property_read_u32_index(dev->of_node, "reg", 0, &offset);
+	if (ret)
+		return dev_err_probe(dev, ret, "missing first reg offset\n");
+	phy->reg_test_offset = offset;
+
+	ret = of_property_read_u32_index(dev->of_node, "reg", 2, &offset);
+	if (ret)
+		return dev_err_probe(dev, ret, "missing second reg offset\n");
+	phy->reg_ctl_offset = offset;
+
+	phy->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(phy->clk))
+		return dev_err_probe(dev, PTR_ERR(phy->clk),
+				     "failed to get clock\n");
+
+	generic_phy = devm_phy_create(dev, dev->of_node, &k230_usb_phy_ops);
+
+	if (IS_ERR(generic_phy))
+		return dev_err_probe(dev, PTR_ERR(generic_phy),
+				     "failed to create PHY\n");
+
+	phy_set_drvdata(generic_phy, phy);
+
+	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(provider))
+		return dev_err_probe(dev, PTR_ERR(provider),
+				     "failed to register phy provider\n");
+
+	return 0;
+}
+
+static const struct of_device_id k230_usb_phy_of_match[] = {
+	{ .compatible = "canaan,k230-usb-phy" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, k230_usb_phy_of_match);
+
+static struct platform_driver k230_usb_phy_driver = {
+	.probe = k230_usb_phy_probe,
+	.driver = {
+		.name = "k230-usb-phy",
+		.of_match_table = k230_usb_phy_of_match,
+	},
+};
+module_platform_driver(k230_usb_phy_driver);
+
+MODULE_DESCRIPTION("Canaan Kendryte K230 USB 2.0 PHY driver");
+MODULE_AUTHOR("Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>");
+MODULE_LICENSE("GPL");
-- 
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[PATCH 5/5] riscv: dts: canaan: Add syscon and USB nodes for K230

[Jiayu Du]

Add top syscon and USB PHY subdevice nodes, USB0/USB1 dwc2 controller
to K230 DTSI, and enable UART0 and USB0/USB1 in DshanPI DT.

Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
 .../boot/dts/canaan/k230-canmv-dshanpi.dts    | 21 ++++++++
 arch/riscv/boot/dts/canaan/k230.dtsi          | 51 +++++++++++++++++++
 2 files changed, 72 insertions(+)

diff --git a/arch/riscv/boot/dts/canaan/k230-canmv-dshanpi.dts b/arch/riscv/boot/dts/canaan/k230-canmv-dshanpi.dts
index 4f95b534ee87..622d273d723a 100644
--- a/arch/riscv/boot/dts/canaan/k230-canmv-dshanpi.dts
+++ b/arch/riscv/boot/dts/canaan/k230-canmv-dshanpi.dts
@@ -80,3 +80,24 @@ &uart0 {
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&usb0 {
+	vusb_d-supply = <&vdd_3v3>;
+	vusb_a-supply = <&vdd_1v8>;
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "host";
+	vusb_d-supply = <&vdd_3v3>;
+	vusb_a-supply = <&vdd_1v8>;
+	status = "okay";
+};
+
+&usbphy0 {
+	status = "okay";
+};
+
+&usbphy1 {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi
index b815a65e02b9..825728727425 100644
--- a/arch/riscv/boot/dts/canaan/k230.dtsi
+++ b/arch/riscv/boot/dts/canaan/k230.dtsi
@@ -148,5 +148,56 @@ uart4: serial@91404000 {
 			reg-shift = <2>;
 			status = "disabled";
 		};
+
+		usb0: usb@91500000 {
+			compatible = "canaan,k230-usb", "snps,dwc2";
+			reg = <0x0 0x91500000 0x0 0x40000>;
+			interrupts = <173 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk K230_USB_480M_RATE>;
+			clock-names = "otg";
+			g-rx-fifo-size = <512>;
+			g-np-tx-fifo-size = <64>;
+			g-tx-fifo-size = <512 1024 64 64 64 64>;
+			phys = <&usbphy0>;
+			phy-names = "usb2-phy";
+			status = "disabled";
+		};
+
+		usb1: usb@91540000 {
+			compatible = "canaan,k230-usb", "snps,dwc2";
+			reg = <0x0 0x91540000 0x0 0x40000>;
+			interrupts = <174 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk K230_USB_480M_RATE>;
+			clock-names = "otg";
+			g-rx-fifo-size = <512>;
+			g-np-tx-fifo-size = <64>;
+			g-tx-fifo-size = <512 1024 64 64 64 64>;
+			phys = <&usbphy1>;
+			phy-names = "usb2-phy";
+			status = "disabled";
+		};
+
+		hi_sys_config: syscon@91585000 {
+			compatible = "canaan,k230-hisys-cfg", "syscon", "simple-mfd";
+			reg = <0x0 0x91585000 0x0 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			usbphy0: usb-phy@70 {
+				compatible = "canaan,k230-usb-phy";
+				reg = <0x70 0x1C>, <0xb0 0x8>;
+				clocks = <&sysclk K230_HS_USB0_AHB_GATE>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
+			usbphy1: usb-phy@90 {
+				compatible = "canaan,k230-usb-phy";
+				reg = <0x90 0x1C>, <0xb8 0x8>;
+				clocks = <&sysclk K230_HS_USB1_AHB_GATE>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
 	};
 };
-- 
2.52.0


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Re: [PATCH 3/5] dt-bindings: usb: dwc2: Add support for Canaan K230 SoC

[Rob Herring (Arm)]

On Tue, 30 Dec 2025 10:37:22 +0800, Jiayu Du wrote:
> Add 'canaan,k230-usb' compatible string with 'snps,dwc2' as fallback
> for the DWC2 IP which is used by Canaan K230.
> 
> Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/usb/dwc2.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml: Unresolvable reference: schemas/phy/canaan,k230-usb-phy.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml: properties:reg: {'description': 'Two register regions for USB PHY in HiSysConfig syscon block.', 'items': [{'description': 'USB PHY test control reg (pullup/pulldown config)'}, {'description': 'USB PHY core control reg (PLL/transceiver tuning)'}], 'minItems': 2, 'maxItems': 2} should not be valid under {'required': ['maxItems']}
	hint: "maxItems" is not needed with an "items" list
	from schema $id: http://devicetree.org/meta-schemas/items.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml: properties:reg: 'oneOf' conditional failed, one must be fixed:
	False schema does not allow 2
	[{'description': 'USB PHY test control reg (pullup/pulldown config)'}, {'description': 'USB PHY core control reg (PLL/transceiver tuning)'}] is too long
	[{'description': 'USB PHY test control reg (pullup/pulldown config)'}, {'description': 'USB PHY core control reg (PLL/transceiver tuning)'}] is too short
	1 was expected
	hint: "minItems" is only needed if less than the "items" list length
	from schema $id: http://devicetree.org/meta-schemas/items.yaml
Lexical error: Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.example.dts:27.35-56 Unexpected 'K230_HS_USB0_AHB_GATE'
Lexical error: Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.example.dts:34.35-56 Unexpected 'K230_HS_USB1_AHB_GATE'
FATAL ERROR: Syntax error parsing input tree
make[2]: *** [scripts/Makefile.dtbs:145: Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1565: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20251230023725.15966-4-jiayu.riscv@isrc.iscas.ac.cn

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


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Re: [PATCH 2/5] dt-bindings: soc: canaan: Add top syscon for Canaan K230 SoC

[Rob Herring (Arm)]

On Tue, 30 Dec 2025 10:37:21 +0800, Jiayu Du wrote:
> The Canaan K230 SoC top system controller provides register access
> to configure related modules. It includes a USB2 PHY and eMMC/SDIO PHY.
> 
> Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> ---
>  .../soc/canaan/canaan,k230-hisys-cfg.yaml     | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml: Unresolvable reference: schemas/phy/canaan,k230-usb-phy.yaml#
Lexical error: Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.example.dts:27.35-56 Unexpected 'K230_HS_USB0_AHB_GATE'
Lexical error: Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.example.dts:34.35-56 Unexpected 'K230_HS_USB1_AHB_GATE'
FATAL ERROR: Syntax error parsing input tree
make[2]: *** [scripts/Makefile.dtbs:145: Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1565: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20251230023725.15966-3-jiayu.riscv@isrc.iscas.ac.cn

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


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Re: [PATCH 1/5] dt-bindings: phy: Add Canaan K230 USB2.0 PHY DT schema

[Krzysztof Kozlowski]

On Tue, Dec 30, 2025 at 10:37:20AM +0800, Jiayu Du wrote:
> k230-usb-phy driver supports USB 2.0 phys integrated in Canaan

Describe hardware, not driver.

> K230 SoC. Add YAML schema for its binding.

There is no such stuff as YAML schema for a binding. Look at other
commits how they phrase it.

> 
> Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> ---
>  .../bindings/phy/canaan,k230-usb-phy.yaml     | 36 +++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml b/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
> new file mode 100644
> index 000000000000..f1c9511c873f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
> @@ -0,0 +1,36 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/canaan,k230-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Canaan K230 USB2.0 PHY
> +
> +maintainers:
> +  - Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> +
> +properties:
> +  compatible:
> +    const: canaan,k230-usb-phy
> +
> +  reg:
> +    description:
> +      Two register regions for USB PHY in HiSysConfig syscon block.

Drop

> +    items:
> +      - description: USB PHY test control reg (pullup/pulldown config)
> +      - description: USB PHY core control reg (PLL/transceiver tuning)
> +    minItems: 2
> +    maxItems: 2

You didn't ever test it, did you? Drop last two lines.

> +
> +  clocks:
> +    maxItems: 1
> +
> +  "#phy-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg

clocks

> +  - "#phy-cells"
> +
> +additionalProperties: false

Missing example.

> -- 
> 2.52.0
> 

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Re: [PATCH 2/5] dt-bindings: soc: canaan: Add top syscon for Canaan K230 SoC

[Krzysztof Kozlowski]

On Tue, Dec 30, 2025 at 10:37:21AM +0800, Jiayu Du wrote:
> The Canaan K230 SoC top system controller provides register access
> to configure related modules. It includes a USB2 PHY and eMMC/SDIO PHY.
> 
> Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> ---
>  .../soc/canaan/canaan,k230-hisys-cfg.yaml     | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml
> 
> diff --git a/Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml b/Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml
> new file mode 100644
> index 000000000000..77875f2d4f48
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/canaan/canaan,k230-hisys-cfg.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/canaan/canaan,k230-hisys-cfg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Canaan K230 HiSysConfig system controller
> +
> +maintainers:
> +  - Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> +
> +description:
> +  The Canaan K230 HiSysConfig system controller provides register access to
> +  configure high-speed peripherals (e.g. eMMC/SDIO PHY tuning) and USB PHY
> +  configuration.
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: canaan,k230-hisys-cfg
> +      - const: syscon
> +      - const: simple-mfd
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1
> +
> +  usb-phy@70:
> +    $ref: schemas/phy/canaan,k230-usb-phy.yaml#

So that's why you did not have example there? But where did you explain
merging strategy/constraints/dependencies? How maintainers can now they
can apply this or not?


> +    unevaluatedProperties: false
> +
> +  usb-phy@90:
> +    $ref: schemas/phy/canaan,k230-usb-phy.yaml#
> +    unevaluatedProperties: false

Anyway, these are not really real children. Defining child per phy,
where each such phy is just few registers, is way too granular. Instead
define one phy with phy-cells=2.

You also MUST make this device - hisys - binding complete. If you do
not, then my review is: fold the children here, because you do not have
any other resources for the parent.

> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    hi_sys_config: syscon@91585000 {
> +        compatible = "canaan,k230-hisys-cfg", "syscon", "simple-mfd";
> +        reg = <0x91585000 0x400>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +
> +        usbphy0: usb-phy@70 {
> +            compatible = "canaan,k230-usb-phy";
> +            reg = <0x70 0x1C>, <0xb0 0x8>;
> +            clocks = <&sysclk K230_HS_USB0_AHB_GATE>;

You never bothered to test your code. Community is not a testing
service. It's your job to TEST IT before sending.

Best regards,
Krzysztof


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Re: [PATCH 1/5] dt-bindings: phy: Add Canaan K230 USB2.0 PHY DT schema

[Jiayu Du]

On Tue, Dec 30, 2025 at 08:36:06AM +0100, Krzysztof Kozlowski wrote:
> On Tue, Dec 30, 2025 at 10:37:20AM +0800, Jiayu Du wrote:
> > k230-usb-phy driver supports USB 2.0 phys integrated in Canaan
> 
> Describe hardware, not driver.
> 
> > K230 SoC. Add YAML schema for its binding.
> 
> There is no such stuff as YAML schema for a binding. Look at other
> commits how they phrase it.
> 
> > 
> > Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
I'm truly sorry for taking up your time. Thank you for your patience.
I will carefully revise and test it.

Regards,
Jiayu Du


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Re: [PATCH 2/5] dt-bindings: soc: canaan: Add top syscon for Canaan K230 SoC

[Jiayu Du]

On Tue, Dec 30, 2025 at 08:39:19AM +0100, Krzysztof Kozlowski wrote:
> On Tue, Dec 30, 2025 at 10:37:21AM +0800, Jiayu Du wrote:
> > The Canaan K230 SoC top system controller provides register access
> > to configure related modules. It includes a USB2 PHY and eMMC/SDIO PHY.
> > 
> > Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
...
> > +
> > +  "#size-cells":
> > +    const: 1
> > +
> > +  usb-phy@70:
> > +    $ref: schemas/phy/canaan,k230-usb-phy.yaml#
> 
> So that's why you did not have example there? But where did you explain
> merging strategy/constraints/dependencies? How maintainers can now they
> can apply this or not?

Sorry, I will update in v2.

> 
> 
> > +    unevaluatedProperties: false
> > +
> > +  usb-phy@90:
> > +    $ref: schemas/phy/canaan,k230-usb-phy.yaml#
> > +    unevaluatedProperties: false
> 
> Anyway, these are not really real children. Defining child per phy,
> where each such phy is just few registers, is way too granular. Instead
> define one phy with phy-cells=2.
> 
> You also MUST make this device - hisys - binding complete. If you do
> not, then my review is: fold the children here, because you do not have
> any other resources for the parent.

This hisys memory area not only includes the usbphy registers,
but also contains the registers of sd/mmc phy. Therefore, the
hisys node is necessary and cannot be folded.


If what I said above is accepted by you, do I still need to
merge the two usb phy nodes by defining one phy with phy-cells=2?

> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    hi_sys_config: syscon@91585000 {
> > +        compatible = "canaan,k230-hisys-cfg", "syscon", "simple-mfd";
> > +        reg = <0x91585000 0x400>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +
> > +        usbphy0: usb-phy@70 {
> > +            compatible = "canaan,k230-usb-phy";
> > +            reg = <0x70 0x1C>, <0xb0 0x8>;
> > +            clocks = <&sysclk K230_HS_USB0_AHB_GATE>;
> 
> You never bothered to test your code. Community is not a testing
> service. It's your job to TEST IT before sending.

Sorry, I've realized this now. I'll test it.

Best regards,
jiayu

>
> Best regards,
> Krzysztof
> 


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Re: [PATCH 2/5] dt-bindings: soc: canaan: Add top syscon for Canaan K230 SoC

[Krzysztof Kozlowski]

On 30/12/2025 14:14, Jiayu Du wrote:
> On Tue, Dec 30, 2025 at 08:39:19AM +0100, Krzysztof Kozlowski wrote:
>> On Tue, Dec 30, 2025 at 10:37:21AM +0800, Jiayu Du wrote:
>>> The Canaan K230 SoC top system controller provides register access
>>> to configure related modules. It includes a USB2 PHY and eMMC/SDIO PHY.
>>>
>>> Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> ...
>>> +
>>> +  "#size-cells":
>>> +    const: 1
>>> +
>>> +  usb-phy@70:
>>> +    $ref: schemas/phy/canaan,k230-usb-phy.yaml#
>>
>> So that's why you did not have example there? But where did you explain
>> merging strategy/constraints/dependencies? How maintainers can now they
>> can apply this or not?
> 
> Sorry, I will update in v2.
> 
>>
>>
>>> +    unevaluatedProperties: false
>>> +
>>> +  usb-phy@90:
>>> +    $ref: schemas/phy/canaan,k230-usb-phy.yaml#
>>> +    unevaluatedProperties: false
>>
>> Anyway, these are not really real children. Defining child per phy,
>> where each such phy is just few registers, is way too granular. Instead
>> define one phy with phy-cells=2.

Just a note: phy-cells=1, I made mistake before.

>>
>> You also MUST make this device - hisys - binding complete. If you do
>> not, then my review is: fold the children here, because you do not have
>> any other resources for the parent.
> 
> This hisys memory area not only includes the usbphy registers,
> but also contains the registers of sd/mmc phy. Therefore, the
> hisys node is necessary and cannot be folded.

Can be. There is absolutely nothing stopping it.

Anyway, define all nodes.

> 
> 
> If what I said above is accepted by you, do I still need to
> merge the two usb phy nodes by defining one phy with phy-cells=2?

You should read your datasheet, not exactly rely on me guessing. In
current form of the binding, you must fold the child into the parent.

Best regards,
Krzysztof

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Re: [PATCH 4/5] phy: usb: Add driver for Canaan K230 USB 2.0 PHY

[Vinod Koul]

On 30-12-25, 10:37, Jiayu Du wrote:
> Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
> initialization, power management and USB mode switching.
> 
> Add Kconfig/Makefile under drivers/phy/canaan/.
> 
> Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> ---
>  drivers/phy/Kconfig               |   1 +
>  drivers/phy/Makefile              |   1 +
>  drivers/phy/canaan/Kconfig        |  14 ++
>  drivers/phy/canaan/Makefile       |   2 +
>  drivers/phy/canaan/phy-k230-usb.c | 272 ++++++++++++++++++++++++++++++
>  5 files changed, 290 insertions(+)
>  create mode 100644 drivers/phy/canaan/Kconfig
>  create mode 100644 drivers/phy/canaan/Makefile
>  create mode 100644 drivers/phy/canaan/phy-k230-usb.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 678dd0452f0a..95e630749350 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig"
>  source "drivers/phy/amlogic/Kconfig"
>  source "drivers/phy/broadcom/Kconfig"
>  source "drivers/phy/cadence/Kconfig"
> +source "drivers/phy/canaan/Kconfig"
>  source "drivers/phy/freescale/Kconfig"
>  source "drivers/phy/hisilicon/Kconfig"
>  source "drivers/phy/ingenic/Kconfig"
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index bfb27fb5a494..f07c68f2e283 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -17,6 +17,7 @@ obj-y					+= allwinner/	\
>  					   amlogic/	\
>  					   broadcom/	\
>  					   cadence/	\
> +					   canaan/	\
>  					   freescale/	\
>  					   hisilicon/	\
>  					   ingenic/	\
> diff --git a/drivers/phy/canaan/Kconfig b/drivers/phy/canaan/Kconfig
> new file mode 100644
> index 000000000000..1ff8831846d5
> --- /dev/null
> +++ b/drivers/phy/canaan/Kconfig
> @@ -0,0 +1,14 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# Phy drivers for Canaan platforms
> +#
> +config PHY_CANAAN_USB
> +	tristate "Canaan USB2 PHY Driver"
> +	depends on (ARCH_CANAAN || COMPILE_TEST) && OF
> +	select GENERIC_PHY
> +	help
> +	Enable this driver to support the USB 2.0 PHY controller
> +	on Canaan K230 RISC-V SoCs. This PHY controller
> +	provides physical layer functionality for USB 2.0 devices.
> +	If you have a Canaan K230 board and need USB 2.0 support,
> +	say Y or M here.
> diff --git a/drivers/phy/canaan/Makefile b/drivers/phy/canaan/Makefile
> new file mode 100644
> index 000000000000..d73857ba284e
> --- /dev/null
> +++ b/drivers/phy/canaan/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +obj-$(CONFIG_PHY_CANAAN_USB)		+= phy-k230-usb.o
> diff --git a/drivers/phy/canaan/phy-k230-usb.c b/drivers/phy/canaan/phy-k230-usb.c
> new file mode 100644
> index 000000000000..668618fb2188
> --- /dev/null
> +++ b/drivers/phy/canaan/phy-k230-usb.c
> @@ -0,0 +1,272 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Canaan usb PHY driver
> + *
> + * Copyright (C) 2025 Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#define TEST_CTL3_OFFSET	0x0C

Lowercase hex values please.. do you need a test register :-)

> +#define CTL0_OFFSET		0x00
> +#define CTL1_OFFSET		0x04
> +#define USB_IDPULLUP0		BIT(4)
> +#define USB_DMPULLDOWN0		BIT(8)
> +#define USB_DPPULLDOWN0		BIT(9)
> +
> +/* USB control register 0 in HiSysConfig system controller */
> +/* PLL Integral Path Tune */
> +#define USB_CTL0_PLLITUNE_MASK		GENMASK(23, 22)
> +
> +/* PLL Proportional Path Tune */
> +#define USB_CTL0_PLLPTUNE_MASK		GENMASK(21, 18)
> +
> +/* PLL Bandwidth Adjustment */
> +#define USB_CTL0_PLLBTUNE_MASK		GENMASK(17, 17)
> +
> +/* VReg18 Bypass Control */
> +#define USB_CTL0_VREGBYPASS_MASK	GENMASK(16, 16)
> +
> +/* Retention Mode Enable */
> +#define USB_CTL0_RETENABLEN_MASK	GENMASK(15, 15)
> +
> +/* Reserved Request Input */
> +#define USB_CTL0_RESREQIN_MASK		GENMASK(14, 14)
> +
> +/* External VBUS Valid Select */
> +#define USB_CTL0_VBUSVLDEXTSEL0_MASK	GENMASK(13, 13)
> +
> +/* OTG Block Disable Control */
> +#define USB_CTL0_OTGDISABLE0_MASK	GENMASK(12, 12)
> +
> +/* Drive VBUS Enable */
> +#define USB_CTL0_DRVVBUS0_MASK		GENMASK(11, 11)
> +
> +/* Autoresume Mode Enable */
> +#define USB_CTL0_AUTORSMENB0_MASK	GENMASK(10, 10)
> +
> +/* HS Transceiver Asynchronous Control */
> +#define USB_CTL0_HSXCVREXTCTL0_MASK	GENMASK(9, 9)
> +
> +/* USB 1.1 Transmit Data */
> +#define USB_CTL0_FSDATAEXT0_MASK	GENMASK(8, 8)
> +
> +/* USB 1.1 SE0 Generation */
> +#define USB_CTL0_FSSE0EXT0_MASK		GENMASK(7, 7)
> +
> +/* USB 1.1 Data Enable */
> +#define USB_CTL0_TXENABLEN0_MASK	GENMASK(6, 6)
> +
> +/* Disconnect Threshold */
> +#define USB_CTL0_COMPDISTUNE0_MASK	GENMASK(5, 3)
> +
> +/* Squelch Threshold */
> +#define USB_CTL0_SQRXTUNE0_MASK		GENMASK(2, 0)
> +
> +/* USB control register 1 in HiSysConfig system controller */
> +/* Data Detect Voltage */
> +#define USB_CTL1_VDATREFTUNE0_MASK	GENMASK(23, 22)
> +
> +/* VBUS Valid Threshold */
> +#define USB_CTL1_OTGTUNE0_MASK		GENMASK(21, 19)
> +
> +/* Transmitter High-Speed Crossover */
> +#define USB_CTL1_TXHSXVTUNE0_MASK	GENMASK(18, 17)
> +
> +/* FS/LS Source Impedance */
> +#define USB_CTL1_TXFSLSTUNE0_MASK	GENMASK(16, 13)
> +
> +/* HS DC Voltage Level */
> +#define USB_CTL1_TXVREFTUNE0_MASK	GENMASK(12, 9)
> +
> +/* HS Transmitter Rise/Fall Time */
> +#define USB_CTL1_TXRISETUNE0_MASK	GENMASK(8, 7)
> +
> +/* USB Source Impedance */
> +#define USB_CTL1_TXRESTUNE0_MASK	GENMASK(6, 5)
> +
> +/* HS Transmitter Pre-Emphasis Current Control */
> +#define USB_CTL1_TXPREEMPAMPTUNE0_MASK	GENMASK(4, 3)
> +
> +/* HS Transmitter Pre-Emphasis Duration Control */
> +#define USB_CTL1_TXPREEMPPULSETUNE0_MASK	GENMASK(2, 2)
> +
> +/* charging detection */
> +#define USB_CTL1_CHRGSRCPUENB0_MASK	GENMASK(1, 0)
> +
> +#define K230_PHY_CTL0_VAL \
> +( \
> +	FIELD_PREP(USB_CTL0_PLLITUNE_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL0_PLLPTUNE_MASK, 0xC) | \

lower hex here and rest

> +	FIELD_PREP(USB_CTL0_PLLBTUNE_MASK, 0x1) | \
> +	FIELD_PREP(USB_CTL0_VREGBYPASS_MASK, 0x1) | \
> +	FIELD_PREP(USB_CTL0_RETENABLEN_MASK, 0x1) | \
> +	FIELD_PREP(USB_CTL0_RESREQIN_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL0_VBUSVLDEXTSEL0_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL0_OTGDISABLE0_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL0_DRVVBUS0_MASK, 0x1) | \
> +	FIELD_PREP(USB_CTL0_AUTORSMENB0_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL0_HSXCVREXTCTL0_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL0_FSDATAEXT0_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL0_FSSE0EXT0_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL0_TXENABLEN0_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL0_COMPDISTUNE0_MASK, 0x3) | \
> +	FIELD_PREP(USB_CTL0_SQRXTUNE0_MASK, 0x3) \
> +)
> +
> +#define K230_PHY_CTL1_VAL \
> +( \
> +	FIELD_PREP(USB_CTL1_VDATREFTUNE0_MASK, 0x1) | \
> +	FIELD_PREP(USB_CTL1_OTGTUNE0_MASK, 0x3) | \
> +	FIELD_PREP(USB_CTL1_TXHSXVTUNE0_MASK, 0x3) | \
> +	FIELD_PREP(USB_CTL1_TXFSLSTUNE0_MASK, 0x3) | \
> +	FIELD_PREP(USB_CTL1_TXVREFTUNE0_MASK, 0x3) | \
> +	FIELD_PREP(USB_CTL1_TXRISETUNE0_MASK, 0x1) | \
> +	FIELD_PREP(USB_CTL1_TXRESTUNE0_MASK, 0x1) | \
> +	FIELD_PREP(USB_CTL1_TXPREEMPAMPTUNE0_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL1_TXPREEMPPULSETUNE0_MASK, 0x0) | \
> +	FIELD_PREP(USB_CTL1_CHRGSRCPUENB0_MASK, 0x0) \
> +)
> +
> +struct k230_usb_phy {
> +	struct regmap *regmap;
> +	u32 reg_ctl_offset;
> +	u32 reg_test_offset;
> +	struct clk *clk;
> +};
> +
> +static int k230_usb_phy_power_on(struct phy *_phy)
> +{
> +	struct k230_usb_phy *phy = phy_get_drvdata(_phy);
> +	int ret;
> +	u32 val;
> +
> +	ret = clk_prepare_enable(phy->clk);
> +	if (ret)
> +		return ret;
> +
> +	ret = regmap_write(phy->regmap, phy->reg_ctl_offset + CTL0_OFFSET,
> +			   K230_PHY_CTL0_VAL);
> +	if (ret)
> +		goto err_disable_clk;
> +
> +	ret = regmap_write(phy->regmap, phy->reg_ctl_offset + CTL1_OFFSET,
> +			   K230_PHY_CTL1_VAL);
> +	if (ret)
> +		goto err_disable_clk;
> +
> +	val |= USB_IDPULLUP0 | USB_DMPULLDOWN0 | USB_DPPULLDOWN0;
> +
> +	ret = regmap_update_bits(phy->regmap, phy->reg_test_offset +
> +				 TEST_CTL3_OFFSET, val, val);

so we are writing to a test register..?

> +	if (ret)
> +		goto err_disable_clk;
> +
> +	return 0;
> +
> +err_disable_clk:
> +	clk_disable_unprepare(phy->clk);
> +	return ret;
> +}
> +
> +static int k230_usb_phy_power_off(struct phy *_phy)
> +{
> +	struct k230_usb_phy *phy = phy_get_drvdata(_phy);
> +	int ret;
> +	u32 val;
> +
> +	val = USB_DMPULLDOWN0 | USB_DPPULLDOWN0;
> +
> +	ret = regmap_update_bits(phy->regmap, phy->reg_test_offset +
> +				 TEST_CTL3_OFFSET, val, 0);
> +	if (ret)
> +		return ret;
> +
> +	clk_disable_unprepare(phy->clk);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops k230_usb_phy_ops = {
> +	.power_on = k230_usb_phy_power_on,
> +	.power_off = k230_usb_phy_power_off,
> +	.owner = THIS_MODULE,
> +};
> +
> +static int k230_usb_phy_probe(struct platform_device *pdev)
> +{
> +	int ret;
> +	u32 offset;
> +	struct regmap *regmap;
> +	struct phy *generic_phy;
> +	struct k230_usb_phy *phy;
> +	struct phy_provider *provider;
> +	struct device *dev = &pdev->dev;

reverse christmas  tree order would look better...

> +	regmap = syscon_node_to_regmap(dev->parent->of_node);
> +	if (IS_ERR(regmap))
> +		return dev_err_probe(dev, PTR_ERR(regmap),
> +				     "failed to get syscon regmap\n");
> +
> +	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> +	if (!phy)
> +		return -ENOMEM;
> +
> +	phy->regmap = regmap;
> +
> +

why two lines...?

> +	ret = of_property_read_u32_index(dev->of_node, "reg", 0, &offset);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "missing first reg offset\n");
> +	phy->reg_test_offset = offset;
> +
> +	ret = of_property_read_u32_index(dev->of_node, "reg", 2, &offset);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "missing second reg offset\n");
> +	phy->reg_ctl_offset = offset;
> +
> +	phy->clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(phy->clk))
> +		return dev_err_probe(dev, PTR_ERR(phy->clk),
> +				     "failed to get clock\n");
> +
> +	generic_phy = devm_phy_create(dev, dev->of_node, &k230_usb_phy_ops);
> +
> +	if (IS_ERR(generic_phy))
> +		return dev_err_probe(dev, PTR_ERR(generic_phy),
> +				     "failed to create PHY\n");
> +
> +	phy_set_drvdata(generic_phy, phy);
> +
> +	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(provider))
> +		return dev_err_probe(dev, PTR_ERR(provider),
> +				     "failed to register phy provider\n");
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id k230_usb_phy_of_match[] = {
> +	{ .compatible = "canaan,k230-usb-phy" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, k230_usb_phy_of_match);
> +
> +static struct platform_driver k230_usb_phy_driver = {
> +	.probe = k230_usb_phy_probe,
> +	.driver = {
> +		.name = "k230-usb-phy",
> +		.of_match_table = k230_usb_phy_of_match,
> +	},
> +};
> +module_platform_driver(k230_usb_phy_driver);
> +
> +MODULE_DESCRIPTION("Canaan Kendryte K230 USB 2.0 PHY driver");
> +MODULE_AUTHOR("Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>");
> +MODULE_LICENSE("GPL");
> -- 
> 2.52.0

-- 
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Re: [PATCH 4/5] phy: usb: Add driver for Canaan K230 USB 2.0 PHY

[Jiayu Du]

On Thu, Jan 01, 2026 at 04:18:01PM +0530, Vinod Koul wrote:
> On 30-12-25, 10:37, Jiayu Du wrote:
> > Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
> > initialization, power management and USB mode switching.
> > 
> > Add Kconfig/Makefile under drivers/phy/canaan/.
> > 
> > Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
...
> > +#define TEST_CTL3_OFFSET	0x0C
> 
> Lowercase hex values please.. do you need a test register :-)

Sorry, I will convert the hex to lowercase.

In the TRM manual, the registers are named TEST_CTL and they are
used to describe the otg0 phy port control. The TRM manual is here[1].
The description of this register is located on page 1015.

Therefore, I have retained the names as stated in the TRM manual.

Link:
https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
[1]

> > +	FIELD_PREP(USB_CTL0_PLLPTUNE_MASK, 0xC) | \
> 
> lower hex here and rest

I will fix it in v2.

> 
> > +	ret = regmap_update_bits(phy->regmap, phy->reg_test_offset +
> > +				 TEST_CTL3_OFFSET, val, val);
> 
> so we are writing to a test register..?

As I mentioned above, this is actually otg0 phy port control
register.

> > +	int ret;
> > +	u32 offset;
> > +	struct regmap *regmap;
> > +	struct phy *generic_phy;
> > +	struct k230_usb_phy *phy;
> > +	struct phy_provider *provider;
> > +	struct device *dev = &pdev->dev;
> 
> reverse christmas  tree order would look better...

I will fix it in v2.

> > +
> > +
> 
> why two lines...?

I will fix it in v2.

> 
> > +MODULE_LICENSE("GPL");
> > -- 
> > 2.52.0
> 
> -- 
> ~Vinod

Regards,
Jiayu Du


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Re: [PATCH 2/5] dt-bindings: soc: canaan: Add top syscon for Canaan K230 SoC

[Jiayu Du]

On Tue, Dec 30, 2025 at 03:00:26PM +0100, Krzysztof Kozlowski wrote:
> On 30/12/2025 14:14, Jiayu Du wrote:
> > On Tue, Dec 30, 2025 at 08:39:19AM +0100, Krzysztof Kozlowski wrote:
> >> On Tue, Dec 30, 2025 at 10:37:21AM +0800, Jiayu Du wrote:
> > This hisys memory area not only includes the usbphy registers,
> > but also contains the registers of sd/mmc phy. Therefore, the
> > hisys node is necessary and cannot be folded.
> 
> Can be. There is absolutely nothing stopping it.
> 
> Anyway, define all nodes.

I will fold the child into the parent in v2, thanks for your guidance.

> > 
> > 
> > If what I said above is accepted by you, do I still need to
> > merge the two usb phy nodes by defining one phy with phy-cells=2?
> 
> You should read your datasheet, not exactly rely on me guessing. In
> current form of the binding, you must fold the child into the parent.
> 
> Best regards,
> Krzysztof
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv


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