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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 07-01-26, 16:11, Charan Pedumuru wrote: > Convert TI PIPE3 PHY binding to DT schema. > Changes during conversion: > - Define a new pattern 'pciephy' to match nodes defined in DT. > - Drop obsolete "id" property from the schema. > > Signed-off-by: Charan Pedumuru > --- > .../devicetree/bindings/phy/ti,phy-usb3.yaml | 127 +++++++++++++++++++++ > 1 file changed, 127 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml > new file mode 100644 > index 000000000000..41b3828723ae > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml > @@ -0,0 +1,127 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TI PIPE3 PHY Module > + > +maintainers: > + - Kishon Vijay Abraham I That is not correct, please check the current people on TI for this. > + > +description: > + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer) > + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs. > + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3 > + interface standard, which defines a common physical layer for > + high-speed serial interfaces. > + > +properties: > + $nodename: > + pattern: "^(pciephy|usb3phy|phy)(@[0-9a-f]+)?$" > + > + compatible: > + enum: > + - ti,phy-usb3 > + - ti,phy-pipe3-sata > + - ti,phy-pipe3-pcie > + - ti,omap-usb3 > + > + reg: > + minItems: 2 > + maxItems: 3 > + > + reg-names: > + minItems: 2 > + maxItems: 3 > + items: > + enum: > + - phy_rx > + - phy_tx > + - pll_ctrl > + > + "#phy-cells": > + const: 0 > + > + clocks: > + minItems: 2 > + maxItems: 7 > + > + clock-names: > + minItems: 2 > + maxItems: 7 > + items: > + enum: [wkupclk, sysclk, refclk, dpll_ref, > + dpll_ref_m2, phy-div, div-clk] > + > + syscon-phy-power: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Phandle/offset pair to system control module register for PHY > + power on/off. > + > + syscon-pllreset: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Phandle/offset pair to CTRL_CORE_SMA_SW_0 register containing > + SATA_PLL_SOFT_RESET bit (SATA PHY only). > + > + syscon-pcs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Phandle/offset pair to system control module for writing PCS delay value. > + > + ctrl-module: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle of control module for PHY power on. > + deprecated: true > + > +dependencies: > + syscon-pllreset: > + properties: > + compatible: > + contains: > + const: ti,phy-pipe3-sata > + > +required: > + - reg > + - compatible > + - reg-names > + - "#phy-cells" > + - clocks > + - clock-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + /* TI PIPE3 USB3 PHY */ > + usb3phy@4a084400 { > + compatible = "ti,phy-usb3"; > + reg = <0x4a084400 0x80>, > + <0x4a084800 0x64>, > + <0x4a084c00 0x40>; > + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; > + #phy-cells = <0>; > + clocks = <&usb_phy_cm_clk32k>, > + <&sys_clkin>, > + <&usb_otg_ss_refclk960m>; > + clock-names = "wkupclk", "sysclk", "refclk"; > + ctrl-module = <&omap_control_usb>; > + }; > + > + - | > + /* TI PIPE3 SATA PHY */ > + phy@4a096000 { > + compatible = "ti,phy-pipe3-sata"; > + reg = <0x4A096000 0x80>, /* phy_rx */ > + <0x4A096400 0x64>, /* phy_tx */ > + <0x4A096800 0x40>; /* pll_ctrl */ > + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; > + clocks = <&sys_clkin1>, <&sata_ref_clk>; > + clock-names = "sysclk", "refclk"; > + syscon-pllreset = <&scm_conf 0x3fc>; > + #phy-cells = <0>; > + }; > +... > > -- > 2.52.0 -- ~Vinod -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy