Re: [PATCH 5/5] arch: arm64: dts: qcom: Add support for PCIe3a

From: Qiang Yu <qiang.yu@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/5] arch: arm64: dts: qcom: Add support for PCIe3a
Date: Thu, 5 Mar 2026 00:40:42 -0800	[thread overview]
Message-ID: <aalBitirfu/rHhIK@hu-qianyu-lv.qualcomm.com> (raw)
In-Reply-To: <u4abdgzrlfijwymnoneb6xa34l3y6fpenlbidvej5cgfz2dzkd@dk37ihalaast>

On Thu, Mar 05, 2026 at 02:02:18AM +0200, Dmitry Baryshkov wrote:
> On Wed, Mar 04, 2026 at 12:21:59AM -0800, Qiang Yu wrote:
> > Describe PCIe3a controller and PHY. Also add required system resources
> > like regulators, clocks, interrupts and registers configuration for PCIe3a.
> > 
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > ---
> >  arch/arm64/boot/dts/qcom/glymur.dtsi | 314 ++++++++++++++++++++++++++++++++++-
> >  1 file changed, 313 insertions(+), 1 deletion(-)
> > 
> > +		pcie3a_phy: phy@f00000 {
> > +			compatible = "qcom,glymur-qmp-gen5x8-pcie-phy";
> > +			reg = <0 0x00f00000 0 0x10000>;
> > +
> > +			clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>,
> > +				 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
> > +				 <&tcsr TCSR_PCIE_3_CLKREF_EN>,
> > +				 <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>,
> > +				 <&gcc GCC_PCIE_3A_PIPE_CLK>,
> > +				 <&gcc GCC_PCIE_PHY_3B_AUX_CLK>;
> > +			clock-names = "aux",
> > +					"cfg_ahb",
> > +					"ref",
> > +					"rchng",
> 
> Please align on "

Okay, will align on " in next version.

> 
> > +					"pipe",
> > +					"phy_b_aux";
> > +
> > +			resets = <&gcc GCC_PCIE_3A_PHY_BCR>,
> > +				 <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>,
> > +				 <&gcc GCC_PCIE_3B_PHY_BCR>,
> > +				 <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>;
> > +			reset-names = "phy",
> > +				      "phy_nocsr",
> > +				      "phy_b",
> > +				      "phy_b_nocsr";
> 
> Should we be supplying _b components by default? What about the
> platforms which might use separate 3a and 3b?

We can override compatible, resets, and clks in board.dts.

- Qiang Yu
> 
> > +
> > +			assigned-clocks = <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>;
> > +			assigned-clock-rates = <100000000>;
> > +
> > +			power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>,
> > +					<&gcc GCC_PCIE_3B_PHY_GDSC>;
> > +
> > +			#clock-cells = <0>;
> > +			clock-output-names = "pcie3a_pipe_clk";
> > +
> > +			#phy-cells = <0>;
> > +
> > +			status = "disabled";
> > +		};
> > +
> >  		pcie4: pci@1bf0000 {
> >  			device_type = "pci";
> >  			compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> > 
> > -- 
> > 2.34.1
> > 
> 
> -- 
> With best wishes
> Dmitry

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