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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2be4f96aec4sm857426eec.25.2026.03.06.01.26.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 01:26:25 -0800 (PST) Date: Fri, 6 Mar 2026 01:26:23 -0800 From: Qiang Yu To: Konrad Dybcio Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/5] phy: qcom: qmp-pcie: Add PCIe Gen5 8-lane bifurcation support for Glymur Message-ID: References: <20260304-glymur_gen5x8_phy-v1-0-849e9a72e125@oss.qualcomm.com> <42a9dd4d-eb96-42c0-b836-dcd7cb9405ff@oss.qualcomm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <42a9dd4d-eb96-42c0-b836-dcd7cb9405ff@oss.qualcomm.com> X-Proofpoint-GUID: lnYlGFomv6qMjfgQpIsi7BYGYhoO-rtU X-Proofpoint-ORIG-GUID: lnYlGFomv6qMjfgQpIsi7BYGYhoO-rtU X-Authority-Analysis: v=2.4 cv=G4wR0tk5 c=1 sm=1 tr=0 ts=69aa9dc3 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=1-162AUNTb8mUwbcPr4A:9 a=CjuIK1q_8ugA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA2MDA4OSBTYWx0ZWRfX+yp2B71cW1vG wQ2FOE1+u3qEJx7+ie5+/ohnwHiB168jY+TyuPJVQ5JTiuUiHL+w1flPp9LD8RWVcVbqPSgui8P DGYRmNIk7eNOyntVWsKPBWhp4xgbLMwBLr67XiS4R1+4TuH8waDv1cc/YOSHfbZFrv8qxBOrpdT 1jRKjP0O0nPNlFKodaDmkfuTCU4xzF87WLSoMUWySEbixGDGwk07W7ozox8k1Z6LLkfUvV/AlWh n4caJu8FFBatDFhXXLXyBj0LjPEmOUPgzk8lvkptiE45NMJH8aVl6kFIdSJY2HeHCfwvCTnUmXN cA9kWGGyhaMEOwfN+VwXrx21wbgXU1Fs4dJvZGZ8xNzGxc2RmuHGVhlNYA2rZxMVUyOXEtA0+Ed y6+4fyuFiTkRCwkGrg18slIUMCFp9oy7l3a79sOdwJftNtIvTqMbX3AOlLojCVJGJGVUFVlhMVf Q8UNuwUN1axbjNALQsw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-06_03,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603060089 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260306_012629_713951_48FDDCB5 X-CRM114-Status: GOOD ( 21.92 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Thu, Mar 05, 2026 at 10:14:05AM +0100, Konrad Dybcio wrote: > On 3/4/26 9:21 AM, Qiang Yu wrote: > > This patch series adds support for PCIe Gen5 8-lane bifurcation mode on > > the Glymur SoC's third PCIe controller. In this configuration, pcie3a PHY > > acts as leader and pcie3b PHY as follower to form a single 8-lane PCIe > > Gen5 interface. > > > > To support 8-lanes mode, this patch series add multiple power domain and > > multi nocsr reset infrastructure as the hardware programming guide > > specifies a strict initialization sequence for bifurcation mode that > > requires coordinated multi-PHY resource management: > > > > 1. Turn on both pcie3a_phy_gdsc and pcie3b_phy_gdsc power domains > > 2. Assert both pcie3a and pcie3b nocsr resets, then deassert them together > > 3. Enable all pcie3a PHY clocks and pcie3b PHY aux clock (bifur_aux) > > 4. Poll for PHY ready status > > I think we never concluded the discussion where I suggested the > bifurcated PHY may be better expressed as a single node with > #phy-cells = <1>, removing the need for duplicated resource references > I understand your suggestion would look like below. I agree that the unified PHY approach being more elegant from a device tree perspective, provide better DT flexibility and eliminate the need for different compatibles and dupicated resources between 1x8 and 2x4 modes. However, this will include implementation complexity to phy driver. The driver would need conditional logic to selectively enable different clocks/resets based on the PHY parameter and maintain mode-specific resource arrays. There's also the issue that assigned-clocks GCC_PCIE_3A_PHY_RCHNG_CLK and GCC_PCIE_3B_PHY_RCHNG_CLK will be set before probe no matter which mode is used, even though in 1x8 mode or only one of them is actually needed. For pipe clock outputs, only pcie3a_pipe_clk would be needed in 1x8 mode while pcie3b_pipe_clk would be unused. For powerdomain, we also need to add additional logic to attach and turn on/off them. While these challenges could be resolved, I'm not sure the benefits justify the added complexity. pcie3_unified_phy { compatible = "qcom,glymur-qmp-gen5-pcie-phy"; reg = <0 0x00f00000 0 0x10000>, <0 0x00f10000 0 0x10000>; /* Both PHY ranges */ clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_3_CLKREF_EN>, <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3A_PIPE_CLK>, <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3B_PIPE_CLK>, <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>, <&gcc GCC_PCIE_3B_PHY_GDSC>; resets = <&gcc GCC_PCIE_3A_PHY_BCR>, <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, <&gcc GCC_PCIE_3B_PHY_BCR>, <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; #clock-cells = <1>; clock-output-names = "pcie3a_pipe_clk", "pcie3b_pipe_clk"; assigned-clocks = <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>, <100000000>; #phy-cells = <1>; /* Parameter: 0=PHY_A, 1=PHY_B, 2=UNIFIED_8LANE */ }; For 2x4 mode (independent 4-lane PHYs): &pcie3a { phys = <&pcie3_unified_phy PHY_A>; /* PHY A only */ status = "okay"; }; &pcie3b { phys = <&pcie3_unified_phy PHY_B>; /* PHY B only */ status = "okay"; }; For 1x8 mode (unified 8-lane PHY): &pcie3a { phys = <&pcie3_unified_phy PHY_AB>; num-lanes = <8>; status = "okay"; }; &pcie3b { status = "disabled"; }; - Qiang Yu -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy