Re: [PATCH v2 4/5] phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur

Dmitry Baryshkov
2026-03-24T21:23:27Z

On Mon, Mar 23, 2026 at 12:15:31AM -0700, Qiang Yu wrote:
> The third PCIe controller on Glymur SoC supports 8-lane operation via
> bifurcation of two PHYs (each requires separate power domian, resets and
> aux clk).
>
> Add dedicated reset/no_csr reset list ("phy_b", "phy_b_nocsr") and
> clock ("phy_b_aux") required for 8-lane operation. Introduce new
> glymur_qmp_gen5x8_pciephy_cfg configuration to enable PCIe Gen5 x8 mode.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 30 +++++++++++++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> @@ -4705,6 +4713,23 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = {
> .phy_status = PHYSTATUS_4_20,
> };
>
> +static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg = {
> + .lanes = 8,
> +
> + .offsets = &qmp_pcie_offsets_v8_50,
> +
> + .reset_list = glymur_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(glymur_pciephy_reset_l),
> + .nocsr_reset_list = glymur_pciephy_nocsr_reset_l,
> + .num_nocsr_resets = ARRAY_SIZE(glymur_pciephy_nocsr_reset_l),

Just for my understanding. If it was not the NOCSR case and had to
program the registers, would we have needed to program anything in the
PCIe3B space?

> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> +
> + .regs = pciephy_v8_50_regs_layout,
> +
> + .phy_status = PHYSTATUS_4_20,
> +};
> +
> static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
> {
> const struct qmp_phy_cfg *cfg = qmp->cfg;
> @@ -5483,6 +5508,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
> }, {
> .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy",
> .data = &glymur_qmp_gen5x4_pciephy_cfg,
> + }, {
> + .compatible = "qcom,glymur-qmp-gen5x8-pcie-phy",
> + .data = &glymur_qmp_gen5x8_pciephy_cfg,
> }, {
> .compatible = "qcom,ipq6018-qmp-pcie-phy",
> .data = &ipq6018_pciephy_cfg,
>
> --
> 2.34.1
>

--
With best wishes
Dmitry