* [PATCH v2 1/3] phy: ti: gmii-sel: Add support for SGMII mode
2023-03-09 6:35 [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
@ 2023-03-09 6:35 ` Siddharth Vadapalli
2023-03-09 6:35 ` [PATCH v2 2/3] phy: ti: gmii-sel: Enable SGMII mode for J7200 Siddharth Vadapalli
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Siddharth Vadapalli @ 2023-03-09 6:35 UTC (permalink / raw)
To: vkoul, kishon, rogerq
Cc: linux-phy, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Add support to configure the CPSW MAC's PHY in SGMII mode if the SoC
supports it. The extra_modes member of the phy_gmii_sel_soc_data struct
corresponding to the SoC is used to determine whether or not the SoC
supports SGMII mode.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
drivers/phy/ti/phy-gmii-sel.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 8c667819c39a..5e16d8dd5bee 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -23,6 +23,7 @@
#define AM33XX_GMII_SEL_MODE_RGMII 2
/* J72xx SoC specific definitions for the CONTROL port */
+#define J72XX_GMII_SEL_MODE_SGMII 3
#define J72XX_GMII_SEL_MODE_QSGMII 4
#define J72XX_GMII_SEL_MODE_QSGMII_SUB 6
@@ -106,6 +107,13 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB;
break;
+ case PHY_INTERFACE_MODE_SGMII:
+ if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII)))
+ goto unsupported;
+ else
+ gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII;
+ break;
+
default:
goto unsupported;
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 2/3] phy: ti: gmii-sel: Enable SGMII mode for J7200
2023-03-09 6:35 [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
2023-03-09 6:35 ` [PATCH v2 1/3] phy: ti: gmii-sel: " Siddharth Vadapalli
@ 2023-03-09 6:35 ` Siddharth Vadapalli
2023-03-09 6:35 ` [PATCH v2 3/3] phy: ti: gmii-sel: Enable SGMII mode for J721E Siddharth Vadapalli
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Siddharth Vadapalli @ 2023-03-09 6:35 UTC (permalink / raw)
To: vkoul, kishon, rogerq
Cc: linux-phy, linux-kernel, linux-arm-kernel, srk, s-vadapalli
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
drivers/phy/ti/phy-gmii-sel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 5e16d8dd5bee..f3da6b020247 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -221,7 +221,7 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
.num_ports = 4,
.num_qsgmii_main_ports = 1,
};
--
2.25.1
--
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 3/3] phy: ti: gmii-sel: Enable SGMII mode for J721E
2023-03-09 6:35 [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
2023-03-09 6:35 ` [PATCH v2 1/3] phy: ti: gmii-sel: " Siddharth Vadapalli
2023-03-09 6:35 ` [PATCH v2 2/3] phy: ti: gmii-sel: Enable SGMII mode for J7200 Siddharth Vadapalli
@ 2023-03-09 6:35 ` Siddharth Vadapalli
2023-04-04 7:04 ` [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Siddharth Vadapalli @ 2023-03-09 6:35 UTC (permalink / raw)
To: vkoul, kishon, rogerq
Cc: linux-phy, linux-kernel, linux-arm-kernel, srk, s-vadapalli
TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
drivers/phy/ti/phy-gmii-sel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index f3da6b020247..c87118cb2af9 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -230,7 +230,7 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
.num_ports = 8,
.num_qsgmii_main_ports = 2,
};
--
2.25.1
--
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^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode
2023-03-09 6:35 [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
` (2 preceding siblings ...)
2023-03-09 6:35 ` [PATCH v2 3/3] phy: ti: gmii-sel: Enable SGMII mode for J721E Siddharth Vadapalli
@ 2023-04-04 7:04 ` Siddharth Vadapalli
2023-04-04 12:13 ` Roger Quadros
2023-05-16 14:31 ` Vinod Koul
5 siblings, 0 replies; 7+ messages in thread
From: Siddharth Vadapalli @ 2023-04-04 7:04 UTC (permalink / raw)
To: vkoul, kishon, rogerq
Cc: linux-phy, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Hello,
This series applies cleanly as of next-20230404. Please merge this series
followed by the series at:
https://lore.kernel.org/r/20230331062521.529005-1-s-vadapalli@ti.com/
in case of no concerns.
Regards,
Siddharth.
On 09/03/23 12:05, Siddharth Vadapalli wrote:
> Hello,
>
> This series adds support to configure the CPSW MAC's PHY in SGMII mode.
> Also, SGMII mode is enabled for TI's J7200 and J721E SoCs.
>
> Changes from v1:
> 1. Add "break" statement within "case PHY_INTERFACE_MODE_SGMII".
> 2. Add newline before "default" case.
> 3. Update commit message of patch 1/3 to follow the existing convention.
>
> v1:
> https://lore.kernel.org/r/20230309062237.389444-1-s-vadapalli@ti.com/
>
> Siddharth Vadapalli (3):
> phy: ti: gmii-sel: Add support for SGMII mode
> phy: ti: gmii-sel: Enable SGMII mode for J7200
> phy: ti: gmii-sel: Enable SGMII mode for J721E
>
> drivers/phy/ti/phy-gmii-sel.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
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^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode
2023-03-09 6:35 [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
` (3 preceding siblings ...)
2023-04-04 7:04 ` [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
@ 2023-04-04 12:13 ` Roger Quadros
2023-05-16 14:31 ` Vinod Koul
5 siblings, 0 replies; 7+ messages in thread
From: Roger Quadros @ 2023-04-04 12:13 UTC (permalink / raw)
To: Siddharth Vadapalli, vkoul, kishon
Cc: linux-phy, linux-kernel, linux-arm-kernel, srk
On 09/03/2023 08:35, Siddharth Vadapalli wrote:
> Hello,
>
> This series adds support to configure the CPSW MAC's PHY in SGMII mode.
> Also, SGMII mode is enabled for TI's J7200 and J721E SoCs.
>
> Changes from v1:
> 1. Add "break" statement within "case PHY_INTERFACE_MODE_SGMII".
> 2. Add newline before "default" case.
> 3. Update commit message of patch 1/3 to follow the existing convention.
>
> v1:
> https://lore.kernel.org/r/20230309062237.389444-1-s-vadapalli@ti.com/
>
> Siddharth Vadapalli (3):
> phy: ti: gmii-sel: Add support for SGMII mode
> phy: ti: gmii-sel: Enable SGMII mode for J7200
> phy: ti: gmii-sel: Enable SGMII mode for J721E
>
> drivers/phy/ti/phy-gmii-sel.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
For the series:
Reviewed-by: Roger Quadros <rogerq@kernel.org>
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^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode
2023-03-09 6:35 [PATCH v2 0/3] PHY-GMII-SEL: Add support for SGMII mode Siddharth Vadapalli
` (4 preceding siblings ...)
2023-04-04 12:13 ` Roger Quadros
@ 2023-05-16 14:31 ` Vinod Koul
5 siblings, 0 replies; 7+ messages in thread
From: Vinod Koul @ 2023-05-16 14:31 UTC (permalink / raw)
To: Siddharth Vadapalli
Cc: kishon, rogerq, linux-phy, linux-kernel, linux-arm-kernel, srk
On 09-03-23, 12:05, Siddharth Vadapalli wrote:
> Hello,
>
> This series adds support to configure the CPSW MAC's PHY in SGMII mode.
> Also, SGMII mode is enabled for TI's J7200 and J721E SoCs.
Applied, thanks
--
~Vinod
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^ permalink raw reply [flat|nested] 7+ messages in thread