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From: "Pandey, Radhey Shyam" <radheys@amd.com>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Cc: vkoul@kernel.org, neil.armstrong@linaro.org,
	michal.simek@amd.com, linux-kernel@vger.kernel.org,
	linux-phy@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org, git@amd.com,
	Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Subject: Re: [PATCH 0/3] phy: zynqmp: fix SERDES scrambler register handling and enable for USB
Date: Tue, 19 May 2026 14:15:20 +0530	[thread overview]
Message-ID: <af789a44-416b-415a-bd41-47d3e46b569f@amd.com> (raw)
In-Reply-To: <20260519082526.GB16205@killaraus.ideasonboard.com>

On 5/19/2026 1:55 PM, Laurent Pinchart wrote:
> Hi Radhey,
> 
> I haven't really been involved with the phy-zynqmp driver for a while,
> despite still being listed as a maintainer. I have just sent a patch
> (you're on CC) to hand maintainership duties over to Tomi Valkeinen, who
> took over maintainership of the ZynqMP DPSUB driver. As Tomi isn't
> really involved with the PHYs, in particular with the non-DP PHYs
> supported by the driver, it could also make more sense for someone from
> AMD to take over maintainer duties for phy-zynqmp.

Thanks for your continued support. As i am handling this driver
internally will send out a patch to also add myself as maintainer.

Thanks,
Radhey>
> On Mon, May 11, 2026 at 10:01:32PM +0530, Radhey Shyam Pandey wrote:
>> This series fixes three related issues in the ZynqMP SERDES PHY
>> scrambler/encoder bypass path:
>>
>> 1. The L0_TM_DISABLE_SCRAMBLE_ENCODER mask incorrectly included bit 2
>>     of L0_TX_DIG_61, which is a reserved read-only field. Correct the
>>     mask to (BIT(3) | GENMASK(1, 0)).
>>
>> 2. xpsgtr_bypass_scrambler_8b10b() used xpsgtr_write_phy() which
>>     performs a full register write, clobbering unrelated bits. Switch
>>     to xpsgtr_clr_set_phy() with clr=mask, set=mask to preserve other
>>     register fields.
>>
>> 3. USB Gen1 requires PHY-side scrambling and 8b/10b encoding as
>>     mandated by the USB 3.x specification. The driver was incorrectly
>>     bypassing these for USB, the same as SATA and SGMII where encoding
>>     is handled in the controller.
>>
>> Nava kishore Manne (3):
>>    phy: zynqmp: fix L0_TM_DISABLE_SCRAMBLE_ENCODER mask
>>    phy: zynqmp: use read-modify-write for SERDES scrambler bypass
>>    phy: zynqmp: keep SERDES scrambler and 8b/10b enabled for USB
>>
>>   drivers/phy/xilinx/phy-zynqmp.c | 37 ++++++++++++++++++++++++++-------
>>   1 file changed, 30 insertions(+), 7 deletions(-)
>>
>>
>> base-commit: 5d6919055dec134de3c40167a490f33c74c12581
> 


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      reply	other threads:[~2026-05-19  8:45 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-11 16:31 [PATCH 0/3] phy: zynqmp: fix SERDES scrambler register handling and enable for USB Radhey Shyam Pandey
2026-05-11 16:31 ` [PATCH 1/3] phy: zynqmp: fix L0_TM_DISABLE_SCRAMBLE_ENCODER mask Radhey Shyam Pandey
2026-05-12 21:35   ` sashiko-bot
2026-05-20 10:37     ` Pandey, Radhey Shyam
2026-05-11 16:31 ` [PATCH 2/3] phy: zynqmp: use read-modify-write for SERDES scrambler bypass Radhey Shyam Pandey
2026-05-11 16:31 ` [PATCH 3/3] phy: zynqmp: keep SERDES scrambler and 8b/10b enabled for USB Radhey Shyam Pandey
2026-05-12 22:31   ` sashiko-bot
2026-05-20 10:22     ` Pandey, Radhey Shyam
2026-05-19  8:25 ` [PATCH 0/3] phy: zynqmp: fix SERDES scrambler register handling and enable " Laurent Pinchart
2026-05-19  8:45   ` Pandey, Radhey Shyam [this message]

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