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Wed, 20 May 2026 15:53:54 -0700 (PDT) X-Received: by 2002:ac8:5d4c:0:b0:50e:6399:eed3 with SMTP id d75a77b69052e-516c54557c3mr7169681cf.20.1779317634055; Wed, 20 May 2026 15:53:54 -0700 (PDT) Received: from redhat.com ([69.43.42.202]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-516514e0b91sm191843371cf.15.2026.05.20.15.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 15:53:52 -0700 (PDT) Date: Wed, 20 May 2026 18:53:51 -0400 From: Brian Masney To: Christian Marangi Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Lorenzo Bianconi , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v8 3/5] clk: en7523: Add support for selecting the Serdes port in SCU Message-ID: References: <20260520150912.11614-1-ansuelsmth@gmail.com> <20260520150912.11614-4-ansuelsmth@gmail.com> MIME-Version: 1.0 In-Reply-To: <20260520150912.11614-4-ansuelsmth@gmail.com> User-Agent: Mutt/2.3.1 (2026-03-20) X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: KTH0qyRqisNAh7hyP3UyAMkJJGfiqECJGQOER7_UvlQ_1779317634 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260520_155358_188749_CF36C64C X-CRM114-Status: GOOD ( 24.72 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi Christian, On Wed, May 20, 2026 at 05:09:08PM +0200, Christian Marangi wrote: > In the SCU register for clock and reset, there are also some register to > select the Serdes port mode. The Airoha AN7581 SoC have 4 different Serdes > that can switch between PCIe, USB or Ethernet mode. > > Add a simple PHY provider that expose the .set_mode OP to toggle the > requested mode for the Serdes port. > > Signed-off-by: Christian Marangi > --- > drivers/clk/Kconfig | 1 + > drivers/clk/clk-en7523.c | 216 ++++++++++++++++++++++++++++++++++++++- > 2 files changed, 214 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index b2efbe9f6acb..e60a824b5117 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -221,6 +221,7 @@ config COMMON_CLK_EN7523 > bool "Clock driver for Airoha/EcoNet SoC system clocks" > depends on OF > depends on ARCH_AIROHA || ECONET || COMPILE_TEST > + select GENERIC_PHY > default ARCH_AIROHA > help > This driver provides the fixed clocks and gates present on Airoha > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > index 1ab0e2eca5d3..d4b73c5f15b9 100644 > --- a/drivers/clk/clk-en7523.c > +++ b/drivers/clk/clk-en7523.c > @@ -6,14 +6,18 @@ > #include > #include > #include > +#include > +#include > #include > #include > #include > +#include > #include > #include > #include > #include > #include > +#include > > #define RST_NR_PER_BANK 32 > > @@ -40,9 +44,22 @@ > #define REG_HIR_MASK GENMASK(31, 16) > /* EN7581 */ > #define REG_NP_SCU_PCIC 0x88 > +#define REG_NP_SCU_SSR3 0x94 > +#define REG_SSUSB_HSGMII_SEL_MASK BIT(29) > +#define REG_SSUSB_HSGMII_SEL_HSGMII FIELD_PREP_CONST(REG_SSUSB_HSGMII_SEL_MASK, 0x0) > +#define REG_SSUSB_HSGMII_SEL_USB FIELD_PREP_CONST(REG_SSUSB_HSGMII_SEL_MASK, 0x1) > #define REG_NP_SCU_SSTR 0x9c > #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) > +#define REG_PCIE_XSI0_SEL_PCIE FIELD_PREP_CONST(REG_PCIE_XSI0_SEL_MASK, 0x0) > +#define REG_PCIE_XSI0_SEL_XFI FIELD_PREP_CONST(REG_PCIE_XSI0_SEL_MASK, 0x1) > +#define REG_PCIE_XSI0_SEL_HSGMII FIELD_PREP_CONST(REG_PCIE_XSI0_SEL_MASK, 0x2) > #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) > +#define REG_PCIE_XSI1_SEL_PCIE FIELD_PREP_CONST(REG_PCIE_XSI1_SEL_MASK, 0x0) > +#define REG_PCIE_XSI1_SEL_XFI FIELD_PREP_CONST(REG_PCIE_XSI1_SEL_MASK, 0x1) > +#define REG_PCIE_XSI1_SEL_HSGMII FIELD_PREP_CONST(REG_PCIE_XSI1_SEL_MASK, 0x2) > +#define REG_USB_PCIE_SEL_MASK BIT(3) > +#define REG_USB_PCIE_SEL_PCIE FIELD_PREP_CONST(REG_USB_PCIE_SEL_MASK, 0x0) > +#define REG_USB_PCIE_SEL_USB FIELD_PREP_CONST(REG_USB_PCIE_SEL_MASK, 0x1) > #define REG_CRYPTO_CLKSRC2 0x20c > /* EN751221 */ > #define EN751221_REG_SPI_DIV 0x0cc > @@ -81,6 +98,8 @@ enum en_hir { > HIR_MAX = 14, > }; > > +#define EN_SERDES_PHY_NUM 4 > + > struct en_clk_desc { > int id; > const char *name; > @@ -113,6 +132,18 @@ struct en_rst_data { > struct reset_controller_dev rcdev; > }; > > +struct en_serdes_phy_instance { > + struct phy *phy; > + unsigned int serdes_port; > +}; > + > +struct en_clk_priv { > + void __iomem *base; > + /* protect SCU register */ > + spinlock_t lock; This spinlock is not initialized with spin_lock_init(). You can do this in en7523_clk_probe() after devm_kzalloc(). With that fixed: Reviewed-by: Brian Masney -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy