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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-907e86d499dsm87767676d6.42.2026.07.28.06.42.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2026 06:42:07 -0700 (PDT) Date: Tue, 28 Jul 2026 09:42:06 -0400 From: Brian Masney To: Stefan =?iso-8859-1?Q?D=F6singer?= Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Vinod Koul , Neil Armstrong , Russell King , Lee Jones , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev Subject: Re: [PATCH v8 06/12] clk: zte: Add regmap-based clocks Message-ID: References: <20260727-zx29clk-v8-0-7a107b00f1dd@gmail.com> <20260727-zx29clk-v8-6-7a107b00f1dd@gmail.com> MIME-Version: 1.0 In-Reply-To: <20260727-zx29clk-v8-6-7a107b00f1dd@gmail.com> User-Agent: Mutt/2.4.0 (2026-06-19) X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: OZVZuybo9yNy4BIKLhXq-uvZY1b1L-9r33JraeAWOf8_1785246130 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260728_064215_416641_08D37BC5 X-CRM114-Status: GOOD ( 29.10 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Mon, Jul 27, 2026 at 09:24:21PM +0300, Stefan D=F6singer wrote: > This is based on meson/clk-regmap.c, although slightly simplified. I > have kept the copyright lines at the top of the file to indicate its > origin. > = > I see that numerous clock drivers have their own incarnation of regmap- > based mux/div/gate clocks. If there is any version of it that is likely > to be elevated to shared code like clk-gate.c I'll copy that and try to > use it as unmodified as possible. > = > Signed-off-by: Stefan D=F6singer > = > --- > = > Version 8: Use ZX297520V3_CLK_NO_EXPORT instead of 0 for unexported clock= s. > = > Version 6: Remove stray regmap (Sashiko) > = > Version 5: Use regmap_test_bits in zte_clk_regmap_gate_is_enabled > --- > drivers/clk/zte/clk-regmap.c | 218 +++++++++++++++++++++++++++++++++++++= +++++- > 1 file changed, 215 insertions(+), 3 deletions(-) > = > diff --git a/drivers/clk/zte/clk-regmap.c b/drivers/clk/zte/clk-regmap.c > index 984abeb45ab2..671b81bcda4d 100644 > --- a/drivers/clk/zte/clk-regmap.c > +++ b/drivers/clk/zte/clk-regmap.c > @@ -7,28 +7,240 @@ > */ > = > #include > +#include > #include > #include > +#include > #include > +#include > +#include > = > #include "clk-zx.h" > = > +struct zte_clk_regmap { > + struct clk_hw hw; > + struct regmap *map; > + u16 reg; > + u8 shift; > + u8 size; > +}; > + > +static inline struct zte_clk_regmap *to_zte_clk_regmap(struct clk_hw *hw) > +{ > + return container_of(hw, struct zte_clk_regmap, hw); > +} > + > +static int zte_clk_regmap_gate_enable(struct clk_hw *hw) > +{ > + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); > + > + return regmap_set_bits(clk->map, clk->reg, BIT(clk->shift)); > +} > + > +static void zte_clk_regmap_gate_disable(struct clk_hw *hw) > +{ > + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); > + > + regmap_clear_bits(clk->map, clk->reg, BIT(clk->shift)); > +} > + > +static int zte_clk_regmap_gate_is_enabled(struct clk_hw *hw) > +{ > + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); > + > + return regmap_test_bits(clk->map, clk->reg, BIT(clk->shift)); > +} > + > +static const struct clk_ops zte_clk_regmap_gate_ops =3D { > + .enable =3D zte_clk_regmap_gate_enable, > + .disable =3D zte_clk_regmap_gate_disable, > + .is_enabled =3D zte_clk_regmap_gate_is_enabled, > +}; > + > int zx_clk_register_gates(struct device *dev, struct regmap *regmap, > const struct zx_gate_desc *desc, unsigned int num, > struct clk_hw_onecell_data *clocks) > { > - return -ENODEV; > + struct zte_clk_regmap *clk; > + unsigned int i; > + int res; > + > + for (i =3D 0; i < num; ++i) { > + struct clk_init_data init =3D {}; > + > + clk =3D devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); > + if (!clk) > + return -ENOMEM; > + > + init.name =3D desc[i].name; > + init.ops =3D &zte_clk_regmap_gate_ops; > + init.parent_names =3D &desc[i].parent; > + init.num_parents =3D 1; > + init.flags =3D CLK_SET_RATE_PARENT | desc[i].flags; > + clk->hw.init =3D &init; > + clk->map =3D regmap; > + clk->reg =3D desc[i].reg; > + clk->shift =3D desc[i].shift; > + clk->size =3D 1; > + > + res =3D devm_clk_hw_register(dev, &clk->hw); > + if (res) > + return dev_err_probe(dev, res, "Failed to register clk %s\n", desc[i]= .name); > + > + if (desc[i].id !=3D ZX297520V3_CLK_NO_EXPORT) > + clocks->hws[desc[i].id] =3D &clk->hw; > + } > + > + return 0; > +} > + > +static unsigned long zte_clk_regmap_div_recalc_rate(struct clk_hw *hw, > + unsigned long prate) > +{ > + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); > + unsigned int val; > + int ret; > + > + ret =3D regmap_read(clk->map, clk->reg, &val); > + if (ret) > + /* Gives a hint that something is wrong */ > + return 0; > + > + val >>=3D clk->shift; > + val &=3D clk_div_mask(clk->size); > + return divider_recalc_rate(hw, prate, val, NULL, 0, clk->size); Newline before the return > +} > + > +static int zte_clk_regmap_div_determine_rate(struct clk_hw *hw, > + struct clk_rate_request *req) > +{ > + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); > + > + return divider_determine_rate(hw, req, NULL, clk->size, 0); > +} > + > +static int zte_clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long = rate, > + unsigned long parent_rate) > +{ > + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); > + unsigned int val; > + int ret; > + > + ret =3D divider_get_val(rate, parent_rate, NULL, clk->size, 0); > + if (ret < 0) > + return ret; > + > + val =3D (unsigned int)ret << clk->shift; > + return regmap_update_bits(clk->map, clk->reg, clk_div_mask(clk->size) <= < clk->shift, val); > } > = > +static const struct clk_ops zte_clk_regmap_divider_ops =3D { > + .recalc_rate =3D zte_clk_regmap_div_recalc_rate, > + .determine_rate =3D zte_clk_regmap_div_determine_rate, > + .set_rate =3D zte_clk_regmap_div_set_rate, > +}; > + > int zx_clk_register_dividers(struct device *dev, struct regmap *regmap, > const struct zx_div_desc *desc, unsigned int num) > { > - return -ENODEV; > + struct zte_clk_regmap *clk; > + unsigned int i; > + int res; > + > + for (i =3D 0; i < num; ++i) { > + struct clk_init_data init =3D {}; > + > + clk =3D devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); > + if (!clk) > + return -ENOMEM; > + > + init.name =3D desc[i].name; > + init.ops =3D &zte_clk_regmap_divider_ops; > + init.parent_names =3D &desc[i].parent; Use parent_data instead of parent_names > + init.num_parents =3D 1; > + init.flags =3D CLK_SET_RATE_PARENT; > + clk->hw.init =3D &init; > + clk->map =3D regmap; > + clk->reg =3D desc[i].reg; > + clk->shift =3D desc[i].shift; > + clk->size =3D desc[i].size; > + > + res =3D devm_clk_hw_register(dev, &clk->hw); > + if (res) > + return dev_err_probe(dev, res, "Failed to register clk %s\n", desc[i]= .name); > + } > + > + return 0; > } > = > +static u8 zte_clk_regmap_mux_get_parent(struct clk_hw *hw) > +{ > + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); > + unsigned int val; > + int ret; > + > + ret =3D regmap_read(clk->map, clk->reg, &val); > + if (ret) > + return 0xff; > + > + val >>=3D clk->shift; > + val &=3D GENMASK(clk->size - 1, 0); > + return clk_mux_val_to_index(hw, NULL, 0, val); > +} > + > +static int zte_clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) > +{ > + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); > + unsigned int val =3D clk_mux_index_to_val(NULL, 0, index); > + > + return regmap_update_bits(clk->map, clk->reg, > + GENMASK(clk->size - 1, 0) << clk->shift, > + val << clk->shift); > +} > + > +static int zte_clk_regmap_mux_determine_rate(struct clk_hw *hw, struct c= lk_rate_request *req) > +{ > + return clk_mux_determine_rate_flags(hw, req, 0); > +} > + > +static const struct clk_ops zte_clk_regmap_mux_ops =3D { > + .get_parent =3D zte_clk_regmap_mux_get_parent, > + .set_parent =3D zte_clk_regmap_mux_set_parent, > + .determine_rate =3D zte_clk_regmap_mux_determine_rate, > +}; > + > int zx_clk_register_muxes(struct device *dev, struct regmap *regmap, > const struct zx_mux_desc *desc, unsigned int num, > struct clk_hw_onecell_data *clocks) > { > - return -ENODEV; > + struct zte_clk_regmap *clk; > + unsigned int i; > + int res; > + > + for (i =3D 0; i < num; ++i) { > + struct clk_init_data init =3D {}; > + > + clk =3D devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); > + if (!clk) > + return -ENOMEM; > + > + init.name =3D desc[i].name; > + init.ops =3D &zte_clk_regmap_mux_ops; > + init.parent_names =3D desc[i].parents; Use parent_data instead of parent_names Brian -- = linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy