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boundary="===============7511867820617891250==" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org --===============7511867820617891250== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="y7ik32cx75s6xqrz" Content-Disposition: inline --y7ik32cx75s6xqrz Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v15 1/6] phy: rockchip: usbdp: Add phy reset notification support MIME-Version: 1.0 Hello Mani, On Sat, Sep 26, 2026 at 09:54:56AM +0200, Manivannan Sadhasivam wrote: > On Tue, Sep 15, 2026 at 05:32:48PM +0200, Sebastian Reichel wrote: > > To resolve issues with running into permanent "cmn ana lcpll lock > > timeout" errors after a few device replugs, add support for reset > > notifications, which will be handled by the DWC3 driver to gracefully > > handle the PHY being disabled. This avoids corrupting the controller's > > internal state and the PIPE interface between the USB3 controller and > > the PHY, thus fixing the issue. > >=20 > > Tested-by: Igor Paunovic # Orange Pi 5 Plus > > Signed-off-by: Sebastian Reichel > > --- > > drivers/phy/rockchip/phy-rockchip-usbdp.c | 19 +++++++++++++++++-- > > 1 file changed, 17 insertions(+), 2 deletions(-) > >=20 > > diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/ro= ckchip/phy-rockchip-usbdp.c > > index e748acdd2d31..0f39982c70b1 100644 > > --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c > > +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c > > @@ -1004,24 +1004,39 @@ static int rk_udphy_power_on(struct rk_udphy *u= dphy, u8 mode) > > } > > =20 > > if (udphy->status =3D=3D UDPHY_MODE_NONE) { > > + phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_PRE_RESET); > > + > > + rk_udphy_u3_port_disable(udphy, true); >=20 > This change is not described in the commit message. Good catch. I'm not sure when that sneaked in. I will split it into its own follow-up patch. FWIW these two things are a little bit interleaved: resetting the PHY results in disabled clocks, results in SError when dwc3 driver tries to access its registers during the PHY reset. This is worked around by the u3 port disabling, which reroutes the clock. But doing that increases the chance a lot, that the PHY does not start up properly again, which requires the reset notifier bits. Greetings, -- Sebastian --y7ik32cx75s6xqrz Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmq6kz0ACgkQ2O7X88g7 +prxFA//RkRn91TuHhTtQSrpWA0YPTIPzbvMilpCIChKhbH++hVwoksGFGltul3o KFh58VDd/huD1gXsKAsMPtDhQLxSgJBy0/MD7HZPhTn6duX3syly5IBaBdt0uAXN 4ys/GBgdfPhO3I6J/6B4oX7dlqgBbMPOMr/rIf6iKhoCGlB+/H/xz69JlZDfxHOj IveJlSGGE7l1K3Q23rjF/tAVJRl6AocqyBSNibyTpDNb2d6nDYl+b3duqrsBcKId i+iibr9lLC8F3yMHGItO/qw7N7eDk9MHNAxUayRItJwf2jLLV6xfcb8JIq804Mup 7gQbazgOa4glMZ6yFHWw/fAgfDPWSLW28FAiei15uQXuFFnuLAVgXaXrVl+1yzcb ui7IFIttv4mo/eFTteA337RgaH5cgvercRqarEOENfZVAMXGReVlfLi2HhT/pFMW 7zdRRq1ylysrhLb00dp8zCaXUS+0WxV6y9WesEt3ICVDCRg22SU6AEL34kerdPt2 95vSn314kdaFNUNV4kPvg3qQsaGlUE162AKVYHSdfHxXFwa3yyfCIk7iBRilIfrJ f6fUBq5glitp2VhpHZW7qoD2vzgXKRlJimggMKsr59U2XawJMe6mb2FH8kOrhkD8 aXCRTzcXghDRMEIfkyZweT5740nurh8oYAD3OlXx234q9nEgUQg= =uXNM -----END PGP SIGNATURE----- --y7ik32cx75s6xqrz-- --===============7511867820617891250== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy --===============7511867820617891250==--