Re: [RFC PATCH v4 2/5] PCI: rockchip: Drop unused custom registers and bitfields

From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Geraldo Nascimento <geraldogabriel@gmail.com>
Cc: linux-rockchip@lists.infradead.org,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH v4 2/5] PCI: rockchip: Drop unused custom registers and bitfields
Date: Fri, 13 Jun 2025 18:25:50 +0300 (EEST)	[thread overview]
Message-ID: <b4dc6d96-b268-7da4-e41f-cc922ae6941c@linux.intel.com> (raw)
In-Reply-To: <aExBeNdkOtFtW87z@geday>

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On Fri, 13 Jun 2025, Geraldo Nascimento wrote:

> On Fri, Jun 13, 2025 at 06:03:14PM +0300, Ilpo Järvinen wrote:
> > On Fri, 13 Jun 2025, Geraldo Nascimento wrote:
> > 
> > > Since we are now using standard PCIe defines, drop
> > > unused custom-defined ones, which are now referenced
> > > from offset at added Capabilities Register.
> > 
> > These are quite short lines, please reflow the changelog paragraphs to the 
> > usual length.
> 
> Hi Ilpo,
> 
> I'll reflow for v5.
> 
> > 
> > > Suggested-By: Bjorn Helgaas <bhelgaas@google.com>
> > > Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> > > ---
> > >  drivers/pci/controller/pcie-rockchip.h | 11 +----------
> > >  1 file changed, 1 insertion(+), 10 deletions(-)
> > > 
> > > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> > > index 5864a20323f2..f611599988d7 100644
> > > --- a/drivers/pci/controller/pcie-rockchip.h
> > > +++ b/drivers/pci/controller/pcie-rockchip.h
> > > @@ -155,16 +155,7 @@
> > >  #define PCIE_EP_CONFIG_DID_VID		(PCIE_EP_CONFIG_BASE + 0x00)
> > >  #define PCIE_EP_CONFIG_LCS		(PCIE_EP_CONFIG_BASE + 0xd0)
> > >  #define PCIE_RC_CONFIG_RID_CCR		(PCIE_RC_CONFIG_BASE + 0x08)
> > > -#define PCIE_RC_CONFIG_DCR		(PCIE_RC_CONFIG_BASE + 0xc4)
> > > -#define   PCIE_RC_CONFIG_DCR_CSPL_SHIFT		18
> > > -#define   PCIE_RC_CONFIG_DCR_CSPL_LIMIT		0xff
> > > -#define   PCIE_RC_CONFIG_DCR_CPLS_SHIFT		26
> > > -#define PCIE_RC_CONFIG_DCSR		(PCIE_RC_CONFIG_BASE + 0xc8)
> > > -#define   PCIE_RC_CONFIG_DCSR_MPS_MASK		GENMASK(7, 5)
> > > -#define   PCIE_RC_CONFIG_DCSR_MPS_256		(0x1 << 5)
> > > -#define PCIE_RC_CONFIG_LINK_CAP		(PCIE_RC_CONFIG_BASE + 0xcc)
> > > -#define   PCIE_RC_CONFIG_LINK_CAP_L0S		BIT(10)
> > > -#define PCIE_RC_CONFIG_LCS		(PCIE_RC_CONFIG_BASE + 0xd0)
> > > +#define PCIE_RC_CONFIG_CR		(PCIE_RC_CONFIG_BASE + 0xc0)
> > 
> > This will cause a build failure because PCIE_RC_CONFIG_CR is used in 1/5 
> > but only introduced here so you'll need to do this in the same patch as 
> > any step within a series must build too. IMO it would anyway make sense to 
> > combine patches 1 & 2.
> 
> Ah, interesting angle. I'll fix it.
> 
> > 
> > >  #define PCIE_EP_CONFIG_LCS		(PCIE_EP_CONFIG_BASE + 0xd0)
> > 
> > Aren't you going to convert this as well?
> 
> I can, but I can't test it however! But I'll Cc: someone who hopefully
> can.

TBH, the risk getting it wrong / changing the resulting object is pretty 
low. :-)

It might be that scripts/objdiff tool could prove there were no changes in 
the binary code output as it looks just a pre-preprocessor change.

-- 
 i.

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