[PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

[PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

[Alex Elder]

This series introduces a PHY driver and a PCIe driver to support PCIe
on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
one PCIe lane, and the other two ports each have two lanes.  All PCIe
ports operate at 5 GT/second.

The PCIe PHYs must be configured using a value that can only be
determined using the combo PHY, operating in PCIe mode.  To allow
that PHY to be used for USB, the needed calibration step is performed
by the PHY driver automatically at probe time.  Once this step is done,
the PHY can be used for either PCIe or USB.

The driver supports 256 MSIs, and initially does not support PCI INTx
interrupts.  The hardware does not support MSI-X.

Version 6 of this series addresses a few comments from Christophe
Jaillet, and improves a workaround that disables ASPM L1.  The two
people who had reported errors on earlier versions of this code have
confirmed their NVMe devices now work when configured with the default
RISC-V kernel configuration.

					-Alex

This series is available here:
  https://github.com/riscstar/linux/tree/outgoing/pcie-v6

Between version 5 and version 6:
  - Aurelien Jarno and Johannes Erdfelt tested this code and found
    they no longer saw the errors they observed previously
  - Disabling ASPM L1 is now done earlier, at the end of the
    dw_pcie_host_ops->init callback rather than ->post_init
  - The function that disables ASPM L1 has been moved and renamed
  - The return value from devm_platform_ioremap_resource_byname()
    is now checked with IS_ERR()
  - The number of MSI vectors implemented is back to 256, after
    confirming with SpacemiT that they are all in fact supported
  - The sentinel entry in the OF match table no longer includes
    a trailing comma
  - MODULE_LICENSE() and MODULE_DESCRIPTION() macros are now
    included

Here is version 5 of this series:
  https://lore.kernel.org/lkml/20251107191557.1827677-1-elder@riscstar.com/

Between version 4 and version 5:
- Clarify that INTx interrupts are not currently supported
- Add Rob Herring's Reviewed-by on patch 3
- The name of the PCIe root port will always begin with "pcie"
- Lines in the bindings are now wrapped at 80 columns
- Subject lines are all captialized (after subsystem tags)
- Place the PCIe Kconfig option in the proper location based on
  vendor name (not Kconfig symbol); expand its description
- Drop two PCIe controller Kconfig dependencies
- Use dw_pcie_readl_dbi() and dw_pcie_writel_dbi() when turning
  off ASPM L1
- The dw_pcie_host_ops->init callback has been rearranged a bit:
    - The vendor and device IDs are now set early
    - PERST# is asserted separate from putting the controller in RC mode
      and indicating power is detected
    - phy_init() is now called later, just before deasserting PERST#
- Because of timing issues involved in having the root port enable power,
  getting and enabling the regulator is back to being done in the PCIe
  controller probe function
- The regulator definition is moved back to the PCIe controller DT node,
  out of the root port sub-node (in "k1-bananapi-f3.dts")

Here is version 4 of this series:
  https://lore.kernel.org/lkml/20251030220259.1063792-1-elder@riscstar.com/

Additional history is available at that link.


Alex Elder (7):
  dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY
  dt-bindings: phy: spacemit: Introduce PCIe PHY
  dt-bindings: pci: spacemit: Introduce PCIe host controller
  phy: spacemit: Introduce PCIe/combo PHY
  PCI: spacemit: Add SpacemiT PCIe host driver
  riscv: dts: spacemit: Add a PCIe regulator
  riscv: dts: spacemit: PCIe and PHY-related updates

 .../bindings/pci/spacemit,k1-pcie-host.yaml   | 157 ++++
 .../bindings/phy/spacemit,k1-combo-phy.yaml   | 114 +++
 .../bindings/phy/spacemit,k1-pcie-phy.yaml    |  71 ++
 .../boot/dts/spacemit/k1-bananapi-f3.dts      |  44 ++
 arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi  |  33 +
 arch/riscv/boot/dts/spacemit/k1.dtsi          | 176 +++++
 drivers/pci/controller/dwc/Kconfig            |  13 +
 drivers/pci/controller/dwc/Makefile           |   1 +
 drivers/pci/controller/dwc/pcie-spacemit-k1.c | 358 ++++++++++
 drivers/phy/Kconfig                           |  11 +
 drivers/phy/Makefile                          |   1 +
 drivers/phy/phy-spacemit-k1-pcie.c            | 670 ++++++++++++++++++
 12 files changed, 1649 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
 create mode 100644 drivers/pci/controller/dwc/pcie-spacemit-k1.c
 create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c


base-commit: 6d7e7251d03f98f26f2ee0dfd21bb0a0480a2178
-- 
2.48.1


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[PATCH v6 1/7] dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY

[Alex Elder]

Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in
the SpacemiT K1 SoC.  This is one of three PCIe PHYs, and is unusual
in that only the combo PHY can perform a calibration step needed to
determine settings used by the other two PCIe PHYs.

Calibration must be done with the combo PHY in PCIe mode, and to allow
this to occur independent of the eventual use for the PHY (PCIe or USB)
some PCIe-related properties must be supplied: clocks; resets; and a
syscon phandle.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
 .../bindings/phy/spacemit,k1-combo-phy.yaml   | 114 ++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
new file mode 100644
index 0000000000000..b59476cd78b57
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe/USB3 Combo PHY
+
+maintainers:
+  - Alex Elder <elder@riscstar.com>
+
+description: >
+  Of the three PHYs on the SpacemiT K1 SoC capable of being used for
+  PCIe, one is a combo PHY that can also be configured for use by a
+  USB 3 controller.  Using PCIe or USB 3 is a board design decision.
+
+  The combo PHY is also the only PCIe PHY that is able to determine
+  PCIe calibration values to use, and this must be determined before
+  the other two PCIe PHYs can be used.  This calibration must be
+  performed with the combo PHY in PCIe mode, and is this is done
+  when the combo PHY is probed.
+
+  The combo PHY uses an external oscillator as a reference clock.
+  During normal operation, the PCIe or USB port driver is responsible
+  for ensuring all other clocks needed by a PHY are enabled, and all
+  resets affecting the PHY are deasserted.  However, for the combo
+  PHY to perform calibration independent of whether it's later used
+  for PCIe or USB, all PCIe mode clocks and resets must be defined.
+
+properties:
+  compatible:
+    const: spacemit,k1-combo-phy
+
+  reg:
+    items:
+      - description: PHY control registers
+
+  clocks:
+    items:
+      - description: External oscillator used by the PHY PLL
+      - description: DWC PCIe Data Bus Interface (DBI) clock
+      - description: DWC PCIe application AXI-bus Master interface clock
+      - description: DWC PCIe application AXI-bus slave interface clock
+
+  clock-names:
+    items:
+      - const: refclk
+      - const: dbi
+      - const: mstr
+      - const: slv
+
+  resets:
+    items:
+      - description: PHY reset; remains deasserted after initialization
+      - description: DWC PCIe Data Bus Interface (DBI) reset
+      - description: DWC PCIe application AXI-bus Master interface reset
+      - description: DWC PCIe application AXI-bus slave interface reset
+
+  reset-names:
+    items:
+      - const: phy
+      - const: dbi
+      - const: mstr
+      - const: slv
+
+  spacemit,apmu:
+    description:
+      A phandle that refers to the APMU system controller, whose
+      regmap is used in setting the mode
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+  "#phy-cells":
+    const: 1
+    description:
+      The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines
+      whether the PHY operates in PCIe or USB3 mode.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - spacemit,apmu
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/spacemit,k1-syscon.h>
+    phy@c0b10000 {
+        compatible = "spacemit,k1-combo-phy";
+        reg = <0xc0b10000 0x1000>;
+        clocks = <&vctcxo_24m>,
+                 <&syscon_apmu CLK_PCIE0_DBI>,
+                 <&syscon_apmu CLK_PCIE0_MASTER>,
+                 <&syscon_apmu CLK_PCIE0_SLAVE>;
+        clock-names = "refclk",
+                      "dbi",
+                      "mstr",
+                      "slv";
+        resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
+                 <&syscon_apmu RESET_PCIE0_DBI>,
+                 <&syscon_apmu RESET_PCIE0_MASTER>,
+                 <&syscon_apmu RESET_PCIE0_SLAVE>;
+        reset-names = "phy",
+                      "dbi",
+                      "mstr",
+                      "slv";
+        spacemit,apmu = <&syscon_apmu>;
+        #phy-cells = <1>;
+    };
-- 
2.48.1


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[PATCH v6 2/7] dt-bindings: phy: spacemit: Introduce PCIe PHY

[Alex Elder]

Add the Device Tree binding for two PCIe PHYs present on the SpacemiT
K1 SoC.  These PHYs are dependent on a separate combo PHY, which
determines at probe time the calibration values used by the PCIe-only
PHYs.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
 .../bindings/phy/spacemit,k1-pcie-phy.yaml    | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
new file mode 100644
index 0000000000000..019b28349be75
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe PHY
+
+maintainers:
+  - Alex Elder <elder@riscstar.com>
+
+description: >
+  Two PHYs on the SpacemiT K1 SoC used for only for PCIe.  These
+  PHYs must be configured using calibration values that are
+  determined by a third "combo PHY".  The combo PHY determines
+  these calibration values during probe so they can be used for
+  the two PCIe-only PHYs.
+
+  The PHY uses an external oscillator as a reference clock.  During
+  normal operation, the PCIe host driver is responsible for ensuring
+  all other clocks needed by a PHY are enabled, and all resets
+  affecting the PHY are deasserted.
+
+properties:
+  compatible:
+    const: spacemit,k1-pcie-phy
+
+  reg:
+    items:
+      - description: PHY control registers
+
+  clocks:
+    items:
+      - description: External oscillator used by the PHY PLL
+
+  clock-names:
+    const: refclk
+
+  resets:
+    items:
+      - description: PHY reset; remains deasserted after initialization
+
+  reset-names:
+    const: phy
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/spacemit,k1-syscon.h>
+    phy@c0c10000 {
+        compatible = "spacemit,k1-pcie-phy";
+        reg = <0xc0c10000 0x1000>;
+        clocks = <&vctcxo_24m>;
+        clock-names = "refclk";
+        resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
+        reset-names = "phy";
+        #phy-cells = <0>;
+    };
-- 
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[PATCH v6 4/7] phy: spacemit: Introduce PCIe/combo PHY

[Alex Elder]

Introduce a driver that supports three PHYs found on the SpacemiT
K1 SoC.  The first PHY is a combo PHY that can be configured for
use for either USB 3 or PCIe.  The other two PHYs support PCIe
only.

All three PHYs must be programmed with an 8 bit receiver termination
value, which must be determined dynamically.  Only the combo PHY is
able to determine this value.  The combo PHY performs a special
calibration step at probe time to discover this, and that value is
used to program each PHY that operates in PCIe mode.  The combo
PHY must therefore be probed before either of the PCIe-only PHYs
will be used.

Each PHY has an internal PLL driven from an external oscillator.
This PLL started when the PHY is first initialized, and stays
on thereafter.

During normal operation, the USB or PCIe driver using the PHY must
ensure (other) clocks and resets are set up properly.

However PCIe mode clocks are enabled and resets are de-asserted
temporarily by this driver to perform the calibration step on the
combo PHY.

Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
 drivers/phy/Kconfig                |  11 +
 drivers/phy/Makefile               |   1 +
 drivers/phy/phy-spacemit-k1-pcie.c | 670 +++++++++++++++++++++++++++++
 3 files changed, 682 insertions(+)
 create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0aa..1984c2e56122e 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -101,6 +101,17 @@ config PHY_NXP_PTN3222
 	  schemes. It supports all three USB 2.0 data rates: Low Speed, Full
 	  Speed and High Speed.
 
+config PHY_SPACEMIT_K1_PCIE
+	tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"
+	depends on ARCH_SPACEMIT || COMPILE_TEST
+	depends on HAS_IOMEM
+	depends on OF
+	select GENERIC_PHY
+	default ARCH_SPACEMIT
+	help
+	  Enable support for the PCIe and USB 3 combo PHY and two
+	  PCIe-only PHYs used in the SpacemiT K1 SoC.
+
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a4942..a206133a35151 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2)		+= phy-snps-eusb2.o
 obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o
 obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o
 obj-$(CONFIG_PHY_NXP_PTN3222)		+= phy-nxp-ptn3222.o
+obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE)	+= phy-spacemit-k1-pcie.o
 obj-y					+= allwinner/	\
 					   amlogic/	\
 					   broadcom/	\
diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/phy-spacemit-k1-pcie.c
new file mode 100644
index 0000000000000..75477bea7f700
--- /dev/null
+++ b/drivers/phy/phy-spacemit-k1-pcie.c
@@ -0,0 +1,670 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SpacemiT K1 PCIe and PCIe/USB 3 combo PHY driver
+ *
+ * Copyright (C) 2025 by RISCstar Solutions Corporation.  All rights reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/phy/phy.h>
+
+/*
+ * Three PCIe ports are supported in the SpacemiT K1 SoC, and this driver
+ * supports their PHYs.
+ *
+ * The PHY for PCIe port A is different from the PHYs for ports B and C:
+ * - It has one lane, while ports B and C have two
+ * - It is a combo PHY can be used for PCIe or USB 3
+ * - It can automatically calibrate PCIe TX and RX termination settings
+ *
+ * The PHY functionality for PCIe ports B and C is identical:
+ * - They have two PCIe lanes (but can be restricted to 1 via device tree)
+ * - They are used for PCIe only
+ * - They are configured using TX and RX values computed for port A
+ *
+ * A given board is designed to use the combo PHY for either PCIe or USB 3.
+ * Whether the combo PHY is configured for PCIe or USB 3 is specified in
+ * device tree using a phandle plus an argument.  The argument indicates
+ * the type (either PHY_TYPE_PCIE or PHY_TYPE_USB3).
+ *
+ * Each PHY has a reset that it gets and deasserts during initialization.
+ * Each depends also on other clocks and resets provided by the controller
+ * hardware (PCIe or USB) it is associated with.  The controller drivers
+ * are required to enable any clocks and de-assert any resets that affect
+ * PHY operation.  In addition each PHY implements an internal PLL, driven
+ * by an external (24 MHz) oscillator.
+ *
+ * PCIe PHYs must be programmed with RX and TX calibration values.  The
+ * combo PHY is the only one that can determine these values.  They are
+ * determined by temporarily enabling the combo PHY in PCIe mode at probe
+ * time (if necessary).  This calibration only needs to be done once, and
+ * when it has completed the TX and RX values are saved.
+ *
+ * To allow the combo PHY to be enabled for calibration, the resets and
+ * clocks it uses in PCIe mode must be supplied.
+ */
+
+struct k1_pcie_phy {
+	struct device *dev;		/* PHY provider device */
+	struct phy *phy;
+	void __iomem *regs;
+	u32 pcie_lanes;			/* Max (1 or 2) unless limited by DT */
+	struct clk *pll;
+	struct clk_hw pll_hw;		/* Private PLL clock */
+
+	/* The remaining fields are only used for the combo PHY */
+	u32 type;			/* PHY_TYPE_PCIE or PHY_TYPE_USB3 */
+	struct regmap *pmu;		/* MMIO regmap (no errors) */
+};
+
+#define CALIBRATION_TIMEOUT		500000	/* For combo PHY (usec) */
+#define PLL_TIMEOUT			500000	/* For PHY PLL lock (usec) */
+#define POLL_DELAY			500	/* Time between polls (usec) */
+
+/* Selecting the combo PHY operating mode requires APMU regmap access */
+#define SYSCON_APMU			"spacemit,apmu"
+
+/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY only) */
+
+#define PMUA_USB_PHY_CTRL0			0x0110
+#define COMBO_PHY_SEL			BIT(3)	/* 0: PCIe; 1: USB 3 */
+
+#define PCIE_CLK_RES_CTRL			0x03cc
+#define PCIE_APP_HOLD_PHY_RST		BIT(30)
+
+/* PHY register space */
+
+/* Offset between lane 0 and lane 1 registers when there are two */
+#define PHY_LANE_OFFSET				0x0400
+
+/* PHY PLL configuration */
+#define PCIE_PU_ADDR_CLK_CFG			0x0008
+#define PLL_READY			BIT(0)		/* read-only */
+#define CFG_INTERNAL_TIMER_ADJ		GENMASK(10, 7)
+#define TIMER_ADJ_USB		0x2
+#define TIMER_ADJ_PCIE		0x6
+#define CFG_SW_PHY_INIT_DONE		BIT(11)	/* We set after PLL config */
+
+#define PCIE_RC_DONE_STATUS			0x0018
+#define CFG_FORCE_RCV_RETRY		BIT(10)		/* Used for PCIe */
+
+/* PCIe PHY lane calibration; assumes 24MHz input clock */
+#define PCIE_RC_CAL_REG2			0x0020
+#define RC_CAL_TOGGLE			BIT(22)
+#define CLKSEL				GENMASK(31, 29)
+#define CLKSEL_24M		0x3
+
+/* Additional PHY PLL configuration (USB 3 and PCIe) */
+#define PCIE_PU_PLL_1				0x0048
+#define REF_100_WSSC			BIT(12)	/* 1: input is 100MHz, SSC */
+#define FREF_SEL			GENMASK(15, 13)
+#define FREF_24M		0x1
+#define SSC_DEP_SEL			GENMASK(19, 16)
+#define SSC_DEP_NONE		0x0
+#define SSC_DEP_5000PPM		0xa
+
+/* PCIe PHY configuration */
+#define PCIE_PU_PLL_2				0x004c
+#define GEN_REF100			BIT(4)	/* 1: generate 100MHz clk */
+
+#define PCIE_RX_REG1				0x0050
+#define EN_RTERM			BIT(3)
+#define AFE_RTERM_REG			GENMASK(11, 8)
+
+#define PCIE_RX_REG2				0x0054
+#define RX_RTERM_SEL			BIT(5)	/* 0: use AFE_RTERM_REG value */
+
+#define PCIE_LTSSM_DIS_ENTRY			0x005c
+#define CFG_REFCLK_MODE			GENMASK(9, 8)
+#define RFCLK_MODE_DRIVER	0x1
+#define OVRD_REFCLK_MODE		BIT(10)	/* 1: use CFG_RFCLK_MODE */
+
+#define PCIE_TX_REG1				0x0064
+#define TX_RTERM_REG			GENMASK(15, 12)
+#define TX_RTERM_SEL			BIT(25)	/* 1: use TX_RTERM_REG */
+
+/* Zeroed for the combo PHY operating in USB mode */
+#define USB3_TEST_CTRL				0x0068
+
+/* PHY calibration values, determined by the combo PHY at probe time */
+#define PCIE_RCAL_RESULT			0x0084	/* Port A PHY only */
+#define RTERM_VALUE_RX			GENMASK(3, 0)
+#define RTERM_VALUE_TX			GENMASK(7, 4)
+#define R_TUNE_DONE			BIT(10)
+
+static u32 k1_phy_rterm = ~0;     /* Invalid initial value */
+
+/* Save the RX and TX receiver termination values */
+static void k1_phy_rterm_set(u32 val)
+{
+	k1_phy_rterm = val & (RTERM_VALUE_RX | RTERM_VALUE_TX);
+}
+
+static bool k1_phy_rterm_valid(void)
+{
+	/* Valid if no bits outside those we care about are set */
+	return !(k1_phy_rterm & ~(RTERM_VALUE_RX | RTERM_VALUE_TX));
+}
+
+static u32 k1_phy_rterm_rx(void)
+{
+	return FIELD_GET(RTERM_VALUE_RX, k1_phy_rterm);
+}
+
+static u32 k1_phy_rterm_tx(void)
+{
+	return FIELD_GET(RTERM_VALUE_TX, k1_phy_rterm);
+}
+
+/* Only the combo PHY has a PMU pointer defined */
+static bool k1_phy_port_a(struct k1_pcie_phy *k1_phy)
+{
+	return !!k1_phy->pmu;
+}
+
+/* The PLL clocks are driven by the external oscillator */
+static const struct clk_parent_data k1_pcie_phy_data[] = {
+	{ .fw_name = "refclk", },
+};
+
+static struct k1_pcie_phy *clk_hw_to_k1_phy(struct clk_hw *clk_hw)
+{
+	return container_of(clk_hw, struct k1_pcie_phy, pll_hw);
+}
+
+/* USB mode only works on the combo PHY, which has only one lane */
+static void k1_pcie_phy_pll_prepare_usb(struct k1_pcie_phy *k1_phy)
+{
+	void __iomem *regs = k1_phy->regs;
+	u32 val;
+
+	val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
+	val &= ~CFG_INTERNAL_TIMER_ADJ;
+	val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_USB);
+	writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
+
+	val = readl(regs + PCIE_PU_PLL_1);
+	val &= ~SSC_DEP_SEL;
+	val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_5000PPM);
+	writel(val, regs + PCIE_PU_PLL_1);
+}
+
+/* Perform PCIe-specific register updates before starting the PLL clock */
+static void k1_pcie_phy_pll_prepare_pcie(struct k1_pcie_phy *k1_phy)
+{
+	void __iomem *regs = k1_phy->regs;
+	u32 val;
+	u32 i;
+
+	for (i = 0; i < k1_phy->pcie_lanes; i++) {
+		val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
+		val &= ~CFG_INTERNAL_TIMER_ADJ;
+		val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_PCIE);
+		writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
+
+		regs += PHY_LANE_OFFSET;	/* Next lane */
+	}
+
+	regs = k1_phy->regs;
+	val = readl(regs + PCIE_RC_DONE_STATUS);
+	val |= CFG_FORCE_RCV_RETRY;
+	writel(val, regs + PCIE_RC_DONE_STATUS);
+
+	val = readl(regs + PCIE_PU_PLL_1);
+	val &= ~SSC_DEP_SEL;
+	val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_NONE);
+	writel(val, regs + PCIE_PU_PLL_1);
+
+	val = readl(regs + PCIE_PU_PLL_2);
+	val |= GEN_REF100;		/* Enable 100 MHz PLL output clock */
+	writel(val, regs + PCIE_PU_PLL_2);
+}
+
+static int k1_pcie_phy_pll_prepare(struct clk_hw *clk_hw)
+{
+	struct k1_pcie_phy *k1_phy = clk_hw_to_k1_phy(clk_hw);
+	void __iomem *regs = k1_phy->regs;
+	u32 val;
+	u32 i;
+
+	if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3)
+		k1_pcie_phy_pll_prepare_usb(k1_phy);
+	else
+		k1_pcie_phy_pll_prepare_pcie(k1_phy);
+
+	/*
+	 * Disable 100 MHz input reference with spread-spectrum
+	 * clocking and select the 24 MHz clock input frequency
+	 */
+	val = readl(regs + PCIE_PU_PLL_1);
+	val &= ~REF_100_WSSC;
+	val &= ~FREF_SEL;
+	val |= FIELD_PREP(FREF_SEL, FREF_24M);
+	writel(val, regs + PCIE_PU_PLL_1);
+
+	/* Mark PLL configuration done on all lanes */
+	for (i = 0; i < k1_phy->pcie_lanes; i++) {
+		val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
+		val |= CFG_SW_PHY_INIT_DONE;
+		writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
+
+		regs += PHY_LANE_OFFSET;	/* Next lane */
+	}
+
+	/*
+	 * Wait for indication the PHY PLL is locked.  Lanes for ports
+	 * B and C share a PLL, so it's enough to sample just lane 0.
+	 */
+	return readl_poll_timeout(k1_phy->regs + PCIE_PU_ADDR_CLK_CFG,
+				  val, val & PLL_READY,
+				  POLL_DELAY, PLL_TIMEOUT);
+}
+
+/* Prepare implies enable, and once enabled, it's always on */
+static const struct clk_ops k1_pcie_phy_pll_ops = {
+	.prepare	= k1_pcie_phy_pll_prepare,
+};
+
+/* We represent the PHY PLL as a private clock */
+static int k1_pcie_phy_pll_setup(struct k1_pcie_phy *k1_phy)
+{
+	struct clk_hw *hw = &k1_phy->pll_hw;
+	struct device *dev = k1_phy->dev;
+	struct clk_init_data init = { };
+	char *name;
+	int ret;
+
+	name = kasprintf(GFP_KERNEL, "pcie%u_phy_pll", k1_phy->phy->id);
+	if (!name)
+		return -ENOMEM;
+
+	init.name = name;
+	init.ops = &k1_pcie_phy_pll_ops;
+	init.parent_data = k1_pcie_phy_data;
+	init.num_parents = ARRAY_SIZE(k1_pcie_phy_data);
+
+	hw->init = &init;
+
+	ret = devm_clk_hw_register(dev, hw);
+
+	kfree(name);	/* __clk_register() duplicates the name we provide */
+
+	if (ret)
+		return ret;
+
+	k1_phy->pll = devm_clk_hw_get_clk(dev, hw, "pll");
+	if (IS_ERR(k1_phy->pll))
+		return PTR_ERR(k1_phy->pll);
+
+	return 0;
+}
+
+/* Select PCIe or USB 3 mode for the combo PHY. */
+static void k1_combo_phy_sel(struct k1_pcie_phy *k1_phy, bool usb)
+{
+	struct regmap *pmu = k1_phy->pmu;
+
+	/* Only change it if it's not already in the desired state */
+	if (!regmap_test_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL) == usb)
+		regmap_assign_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL, usb);
+}
+
+static void k1_pcie_phy_init_pcie(struct k1_pcie_phy *k1_phy)
+{
+	u32 rx_rterm = k1_phy_rterm_rx();
+	u32 tx_rterm = k1_phy_rterm_tx();
+	void __iomem *regs;
+	u32 val;
+	int i;
+
+	/* For the combo PHY, set PHY to PCIe mode */
+	if (k1_phy_port_a(k1_phy))
+		k1_combo_phy_sel(k1_phy, false);
+
+	regs = k1_phy->regs;
+	for (i = 0; i < k1_phy->pcie_lanes; i++) {
+		val = readl(regs + PCIE_RX_REG1);
+
+		/* Set RX analog front-end receiver termination value */
+		val &= ~AFE_RTERM_REG;
+		val |= FIELD_PREP(AFE_RTERM_REG, rx_rterm);
+
+		/* And enable refclock receiver termination */
+		val |= EN_RTERM;
+		writel(val, regs + PCIE_RX_REG1);
+
+		val = readl(regs + PCIE_RX_REG2);
+		/* Use PCIE_RX_REG1 AFE_RTERM_REG value */
+		val &= ~RX_RTERM_SEL;
+		writel(val, regs + PCIE_RX_REG2);
+
+		val = readl(regs + PCIE_TX_REG1);
+
+		/* Set TX driver termination value */
+		val &= ~TX_RTERM_REG;
+		val |= FIELD_PREP(TX_RTERM_REG, tx_rterm);
+
+		/* Use PCIE_TX_REG1 TX_RTERM_REG value */
+		val |= TX_RTERM_SEL;
+		writel(val, regs + PCIE_TX_REG1);
+
+		/* Set the input clock to 24 MHz, and clear RC_CAL_TOGGLE */
+		val = readl(regs + PCIE_RC_CAL_REG2);
+		val &= CLKSEL;
+		val |= FIELD_PREP(CLKSEL, CLKSEL_24M);
+		val &= ~RC_CAL_TOGGLE;
+		writel(val, regs + PCIE_RC_CAL_REG2);
+
+		/* Now trigger recalibration by setting RC_CAL_TOGGLE again */
+		val |= RC_CAL_TOGGLE;
+		writel(val, regs + PCIE_RC_CAL_REG2);
+
+		val = readl(regs + PCIE_LTSSM_DIS_ENTRY);
+		/* Override the reference clock; set to refclk driver mode */
+		val |= OVRD_REFCLK_MODE;
+		val &= ~CFG_REFCLK_MODE;
+		val |= FIELD_PREP(CFG_REFCLK_MODE, RFCLK_MODE_DRIVER);
+		writel(val, regs + PCIE_LTSSM_DIS_ENTRY);
+
+		regs += PHY_LANE_OFFSET;	/* Next lane */
+	}
+}
+
+/* Only called for combo PHY */
+static void k1_pcie_phy_init_usb(struct k1_pcie_phy *k1_phy)
+{
+	k1_combo_phy_sel(k1_phy, true);
+
+	/* We're not doing any testing */
+	writel(0, k1_phy->regs + USB3_TEST_CTRL);
+}
+
+static int k1_pcie_phy_init(struct phy *phy)
+{
+	struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy);
+
+	/* Note: port type is only valid for port A (both checks needed) */
+	if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3)
+		k1_pcie_phy_init_usb(k1_phy);
+	else
+		k1_pcie_phy_init_pcie(k1_phy);
+
+
+	return clk_prepare_enable(k1_phy->pll);
+}
+
+static int k1_pcie_phy_exit(struct phy *phy)
+{
+	struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy);
+
+	clk_disable_unprepare(k1_phy->pll);
+
+	return 0;
+}
+
+static const struct phy_ops k1_pcie_phy_ops = {
+	.init		= k1_pcie_phy_init,
+	.exit		= k1_pcie_phy_exit,
+	.owner		= THIS_MODULE,
+};
+
+/*
+ * Get values needed for calibrating PHYs operating in PCIe mode.  Only
+ * the combo PHY is able to do this, and its calibration values are used
+ * for configuring all PCIe PHYs.
+ *
+ * We always need to de-assert the "global" reset on the combo PHY,
+ * because the USB driver depends on it.  If used for PCIe, that driver
+ * will (also) de-assert this, but by leaving it de-asserted for the
+ * combo PHY, the USB driver doesn't have to do this.  Note: although
+ * SpacemiT refers to this as the global reset, we name the "phy" reset.
+ *
+ * In addition, we guarantee the APP_HOLD_PHY_RESET bit is clear for the
+ * combo PHY, so the USB driver doesn't have to manage that either.  The
+ * PCIe driver is free to change this bit for normal operation.
+ *
+ * Calibration only needs to be done once.  It's possible calibration has
+ * already completed (e.g., it might have happened in the boot loader, or
+ * -EPROBE_DEFER might result in this function being called again).  So we
+ * check that early too, to avoid doing it more than once.
+ *
+ * Otherwise we temporarily power up the PHY using the PCIe app clocks
+ * and resets, wait for the hardware to indicate calibration is done,
+ * grab the value, then shut the PHY down again.
+ */
+static int k1_pcie_combo_phy_calibrate(struct k1_pcie_phy *k1_phy)
+{
+	struct reset_control_bulk_data resets[] = {
+		{ .id = "dbi", },
+		{ .id = "mstr", },
+		{ .id = "slv", },
+	};
+	struct clk_bulk_data clocks[] = {
+		{ .id = "dbi", },
+		{ .id = "mstr", },
+		{ .id = "slv", },
+	};
+	struct device *dev = k1_phy->dev;
+	int ret = 0;
+	int val;
+
+	/* Nothing to do if we already set the receiver termination value */
+	if (k1_phy_rterm_valid())
+		return 0;
+
+	/*
+	 * We also guarantee the APP_HOLD_PHY_RESET bit is clear.  We can
+	 * leave this bit clear even if an error happens below.
+	 */
+	regmap_assign_bits(k1_phy->pmu, PCIE_CLK_RES_CTRL,
+			   PCIE_APP_HOLD_PHY_RST, false);
+
+	/* If the calibration already completed (e.g. by U-Boot), we're done */
+	val = readl(k1_phy->regs + PCIE_RCAL_RESULT);
+	if (val & R_TUNE_DONE)
+		goto out_tune_done;
+
+	/* Put the PHY into PCIe mode */
+	k1_combo_phy_sel(k1_phy, false);
+
+	/* Get and enable the PCIe app clocks */
+	ret = clk_bulk_get(dev, ARRAY_SIZE(clocks), clocks);
+	if (ret < 0)
+		goto out_tune_done;
+	ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
+	if (ret)
+		goto out_put_clocks;
+
+	/* Get the PCIe application resets (not the PHY reset) */
+	ret = reset_control_bulk_get_shared(dev, ARRAY_SIZE(resets), resets);
+	if (ret)
+		goto out_disable_clocks;
+
+	/* De-assert the PCIe application resets */
+	ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets);
+	if (ret)
+		goto out_put_resets;
+
+	/*
+	 * This is the core activity here.  Wait for the hardware to
+	 * signal that it has completed calibration/tuning.  Once it
+	 * has, the register value will contain the values we'll
+	 * use to configure PCIe PHYs.
+	 */
+	ret = readl_poll_timeout(k1_phy->regs + PCIE_RCAL_RESULT,
+				 val, val & R_TUNE_DONE,
+				 POLL_DELAY, CALIBRATION_TIMEOUT);
+
+	/* Clean up.  We're done with the resets and clocks */
+	reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
+out_put_resets:
+	reset_control_bulk_put(ARRAY_SIZE(resets), resets);
+out_disable_clocks:
+	clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
+out_put_clocks:
+	clk_bulk_put(ARRAY_SIZE(clocks), clocks);
+out_tune_done:
+	/* If we got the value without timing out, set k1_phy_rterm */
+	if (!ret)
+		k1_phy_rterm_set(val);
+
+	return ret;
+}
+
+static struct phy *
+k1_pcie_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args)
+{
+	struct k1_pcie_phy *k1_phy = dev_get_drvdata(dev);
+	u32 type;
+
+	/* The argument specifying the PHY mode is required */
+	if (args->args_count != 1)
+		return ERR_PTR(-EINVAL);
+
+	/* We only support PCIe and USB 3 mode */
+	type = args->args[0];
+	if (type != PHY_TYPE_PCIE && type != PHY_TYPE_USB3)
+		return ERR_PTR(-EINVAL);
+
+	/* This PHY can only be used once */
+	if (k1_phy->type != PHY_NONE)
+		return ERR_PTR(-EBUSY);
+
+	k1_phy->type = type;
+
+	return k1_phy->phy;
+}
+
+/* Use the maximum number of PCIe lanes unless limited by device tree */
+static u32 k1_pcie_num_lanes(struct k1_pcie_phy *k1_phy, bool port_a)
+{
+	struct device *dev = k1_phy->dev;
+	u32 count = 0;
+	u32 max;
+	int ret;
+
+	ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &count);
+	if (count == 1)
+		return 1;
+
+	if (count == 2 && !port_a)
+		return 2;
+
+	max = port_a ? 1 : 2;
+	if (ret != -EINVAL)
+		dev_warn(dev, "bad lane count %u for port; using %u\n",
+			 count, max);
+
+	return max;
+}
+
+static int k1_pcie_combo_phy_probe(struct k1_pcie_phy *k1_phy)
+{
+	struct device *dev = k1_phy->dev;
+	struct regmap *regmap;
+	int ret;
+
+	/* Setting the PHY mode requires access to the PMU regmap */
+	regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), SYSCON_APMU);
+	if (IS_ERR(regmap))
+		return dev_err_probe(dev, PTR_ERR(regmap), "failed to get PMU\n");
+	k1_phy->pmu = regmap;
+
+	ret = k1_pcie_combo_phy_calibrate(k1_phy);
+	if (ret)
+		return dev_err_probe(dev, ret, "calibration failed\n");
+
+	/* Needed by k1_pcie_combo_phy_xlate(), which also sets k1_phy->type */
+	dev_set_drvdata(dev, k1_phy);
+
+	return 0;
+}
+
+static int k1_pcie_phy_probe(struct platform_device *pdev)
+{
+	struct phy *(*xlate)(struct device *dev,
+			     const struct of_phandle_args *args);
+	struct device *dev = &pdev->dev;
+	struct reset_control *phy_reset;
+	struct phy_provider *provider;
+	struct k1_pcie_phy *k1_phy;
+	bool probing_port_a;
+	int ret;
+
+	xlate = of_device_get_match_data(dev);
+	probing_port_a = xlate == k1_pcie_combo_phy_xlate;
+
+	/* Only the combo PHY can calibrate, so it must probe first */
+	if (!k1_phy_rterm_valid() && !probing_port_a)
+		return -EPROBE_DEFER;
+
+	k1_phy = devm_kzalloc(dev, sizeof(*k1_phy), GFP_KERNEL);
+	if (!k1_phy)
+		return -ENOMEM;
+	k1_phy->dev = dev;
+
+	k1_phy->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(k1_phy->regs))
+		return dev_err_probe(dev, PTR_ERR(k1_phy->regs),
+				     "error mapping registers\n");
+
+	/* De-assert the PHY (global) reset and leave it that way */
+	phy_reset = devm_reset_control_get_exclusive_deasserted(dev, "phy");
+	if (IS_ERR(phy_reset))
+		return PTR_ERR(phy_reset);
+
+	if (probing_port_a) {
+		ret = k1_pcie_combo_phy_probe(k1_phy);
+		if (ret)
+			return dev_err_probe(dev, ret,
+					     "error probing combo phy\n");
+	}
+
+	k1_phy->pcie_lanes = k1_pcie_num_lanes(k1_phy, probing_port_a);
+
+	k1_phy->phy = devm_phy_create(dev, NULL, &k1_pcie_phy_ops);
+	if (IS_ERR(k1_phy->phy))
+		return dev_err_probe(dev, PTR_ERR(k1_phy->phy),
+				     "error creating phy\n");
+	phy_set_drvdata(k1_phy->phy, k1_phy);
+
+	ret = k1_pcie_phy_pll_setup(k1_phy);
+	if (ret)
+		return dev_err_probe(dev, ret, "error initializing clock\n");
+
+	provider = devm_of_phy_provider_register(dev, xlate);
+	if (IS_ERR(provider))
+		return dev_err_probe(dev, PTR_ERR(provider),
+				     "error registering provider\n");
+	return 0;
+}
+
+static const struct of_device_id k1_pcie_phy_of_match[] = {
+	{ .compatible = "spacemit,k1-combo-phy", k1_pcie_combo_phy_xlate, },
+	{ .compatible = "spacemit,k1-pcie-phy", of_phy_simple_xlate, },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, k1_pcie_phy_of_match);
+
+static struct platform_driver k1_pcie_phy_driver = {
+	.probe	= k1_pcie_phy_probe,
+	.driver = {
+		.of_match_table	= k1_pcie_phy_of_match,
+		.name = "spacemit-k1-pcie-phy",
+	}
+};
+module_platform_driver(k1_pcie_phy_driver);
+
+MODULE_DESCRIPTION("SpacemiT K1 PCIe and USB 3 PHY driver");
+MODULE_LICENSE("GPL");
-- 
2.48.1


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Re: [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

[Aurelien Jarno]

On 2025-11-13 15:45, Alex Elder wrote:
> This series introduces a PHY driver and a PCIe driver to support PCIe
> on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
> Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
> PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
> one PCIe lane, and the other two ports each have two lanes.  All PCIe
> ports operate at 5 GT/second.
> 
> The PCIe PHYs must be configured using a value that can only be
> determined using the combo PHY, operating in PCIe mode.  To allow
> that PHY to be used for USB, the needed calibration step is performed
> by the PHY driver automatically at probe time.  Once this step is done,
> the PHY can be used for either PCIe or USB.
> 
> The driver supports 256 MSIs, and initially does not support PCI INTx
> interrupts.  The hardware does not support MSI-X.
> 
> Version 6 of this series addresses a few comments from Christophe
> Jaillet, and improves a workaround that disables ASPM L1.  The two
> people who had reported errors on earlier versions of this code have
> confirmed their NVMe devices now work when configured with the default
> RISC-V kernel configuration.

Thanks for this new version. I confirm it works fine on the various NVME 
devices for which I reported issues with the previous versions of this 
patchset.

Tested-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                     http://aurel32.net

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Re: [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

[Johannes Erdfelt]

On Thu, Nov 13, 2025, Alex Elder <elder@riscstar.com> wrote:
> This series introduces a PHY driver and a PCIe driver to support PCIe
> on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
> Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
> PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
> one PCIe lane, and the other two ports each have two lanes.  All PCIe
> ports operate at 5 GT/second.
> 
> The PCIe PHYs must be configured using a value that can only be
> determined using the combo PHY, operating in PCIe mode.  To allow
> that PHY to be used for USB, the needed calibration step is performed
> by the PHY driver automatically at probe time.  Once this step is done,
> the PHY can be used for either PCIe or USB.
> 
> The driver supports 256 MSIs, and initially does not support PCI INTx
> interrupts.  The hardware does not support MSI-X.
> 
> Version 6 of this series addresses a few comments from Christophe
> Jaillet, and improves a workaround that disables ASPM L1.  The two
> people who had reported errors on earlier versions of this code have
> confirmed their NVMe devices now work when configured with the default
> RISC-V kernel configuration.

I've tested this latest patchset on my Orange Pi RV2 board. This
patchset now works with the Intel 600p NVME SSD I had previously had
troublw with. Thanks!

Tested-by: Johannes Erdfelt <johannes@erdfelt.com>

JE


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Re: [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

[Jason Montleon]

On Thu, Nov 13, 2025 at 4:45 PM Alex Elder <elder@riscstar.com> wrote:
>
> This series introduces a PHY driver and a PCIe driver to support PCIe
> on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
> Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
> PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
> one PCIe lane, and the other two ports each have two lanes.  All PCIe
> ports operate at 5 GT/second.
>
> The PCIe PHYs must be configured using a value that can only be
> determined using the combo PHY, operating in PCIe mode.  To allow
> that PHY to be used for USB, the needed calibration step is performed
> by the PHY driver automatically at probe time.  Once this step is done,
> the PHY can be used for either PCIe or USB.
>
> The driver supports 256 MSIs, and initially does not support PCI INTx
> interrupts.  The hardware does not support MSI-X.
>
> Version 6 of this series addresses a few comments from Christophe
> Jaillet, and improves a workaround that disables ASPM L1.  The two
> people who had reported errors on earlier versions of this code have
> confirmed their NVMe devices now work when configured with the default
> RISC-V kernel configuration.

I successfully tested this patchset on a Banana Pi F3 and also a
Milk-V M1 Jupiter by making the same additions to k1-milkv-jupiter.dts
as were made to k1-bananapi-f3.dts.
I no longer have problems with NVME devices like I did when I tried v3 and v4.

Tested-by: Jason Montleon <jmontleo@redhat.com>


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Re: (subset) [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

[Manivannan Sadhasivam]

On Thu, 13 Nov 2025 15:45:32 -0600, Alex Elder wrote:
> This series introduces a PHY driver and a PCIe driver to support PCIe
> on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
> Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
> PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
> one PCIe lane, and the other two ports each have two lanes.  All PCIe
> ports operate at 5 GT/second.
> 
> [...]

Applied, thanks!

[3/7] dt-bindings: pci: spacemit: Introduce PCIe host controller
      commit: a812b09a6b599ea80ec1065a9a635724a235843d
[5/7] PCI: spacemit: Add SpacemiT PCIe host driver
      commit: ff64e078e45faee50cc6ca7900a3520e8ff1c79e

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>


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Re: [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

[Alex Elder]

On 11/14/25 10:21 PM, Jason Montleon wrote:
> On Thu, Nov 13, 2025 at 4:45 PM Alex Elder <elder@riscstar.com> wrote:
>>
>> This series introduces a PHY driver and a PCIe driver to support PCIe
>> on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
>> Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
>> PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
>> one PCIe lane, and the other two ports each have two lanes.  All PCIe
>> ports operate at 5 GT/second.
>>
>> The PCIe PHYs must be configured using a value that can only be
>> determined using the combo PHY, operating in PCIe mode.  To allow
>> that PHY to be used for USB, the needed calibration step is performed
>> by the PHY driver automatically at probe time.  Once this step is done,
>> the PHY can be used for either PCIe or USB.
>>
>> The driver supports 256 MSIs, and initially does not support PCI INTx
>> interrupts.  The hardware does not support MSI-X.
>>
>> Version 6 of this series addresses a few comments from Christophe
>> Jaillet, and improves a workaround that disables ASPM L1.  The two
>> people who had reported errors on earlier versions of this code have
>> confirmed their NVMe devices now work when configured with the default
>> RISC-V kernel configuration.
> 
> I successfully tested this patchset on a Banana Pi F3 and also a
> Milk-V M1 Jupiter by making the same additions to k1-milkv-jupiter.dts
> as were made to k1-bananapi-f3.dts.
> I no longer have problems with NVME devices like I did when I tried v3 and v4.
> 
> Tested-by: Jason Montleon <jmontleo@redhat.com>

Thank you very much for testing this.  Your Tested-by is included
in Mani's commit.

					-Alex

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Re: [PATCH v6 4/7] phy: spacemit: Introduce PCIe/combo PHY

[Neil Armstrong]

On 11/13/25 22:45, Alex Elder wrote:
> Introduce a driver that supports three PHYs found on the SpacemiT
> K1 SoC.  The first PHY is a combo PHY that can be configured for
> use for either USB 3 or PCIe.  The other two PHYs support PCIe
> only.
> 
> All three PHYs must be programmed with an 8 bit receiver termination
> value, which must be determined dynamically.  Only the combo PHY is
> able to determine this value.  The combo PHY performs a special
> calibration step at probe time to discover this, and that value is
> used to program each PHY that operates in PCIe mode.  The combo
> PHY must therefore be probed before either of the PCIe-only PHYs
> will be used.
> 
> Each PHY has an internal PLL driven from an external oscillator.
> This PLL started when the PHY is first initialized, and stays
> on thereafter.
> 
> During normal operation, the USB or PCIe driver using the PHY must
> ensure (other) clocks and resets are set up properly.
> 
> However PCIe mode clocks are enabled and resets are de-asserted
> temporarily by this driver to perform the calibration step on the
> combo PHY.
> 
> Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
>   drivers/phy/Kconfig                |  11 +
>   drivers/phy/Makefile               |   1 +
>   drivers/phy/phy-spacemit-k1-pcie.c | 670 +++++++++++++++++++++++++++++
>   3 files changed, 682 insertions(+)
>   create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 678dd0452f0aa..1984c2e56122e 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -101,6 +101,17 @@ config PHY_NXP_PTN3222
>   	  schemes. It supports all three USB 2.0 data rates: Low Speed, Full
>   	  Speed and High Speed.
>   
> +config PHY_SPACEMIT_K1_PCIE
> +	tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"
> +	depends on ARCH_SPACEMIT || COMPILE_TEST
> +	depends on HAS_IOMEM
> +	depends on OF
> +	select GENERIC_PHY
> +	default ARCH_SPACEMIT
> +	help
> +	  Enable support for the PCIe and USB 3 combo PHY and two
> +	  PCIe-only PHYs used in the SpacemiT K1 SoC.
> +
>   source "drivers/phy/allwinner/Kconfig"
>   source "drivers/phy/amlogic/Kconfig"
>   source "drivers/phy/broadcom/Kconfig"
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index bfb27fb5a4942..a206133a35151 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2)		+= phy-snps-eusb2.o
>   obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o
>   obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o
>   obj-$(CONFIG_PHY_NXP_PTN3222)		+= phy-nxp-ptn3222.o
> +obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE)	+= phy-spacemit-k1-pcie.o
>   obj-y					+= allwinner/	\
>   					   amlogic/	\
>   					   broadcom/	\
> diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/phy-spacemit-k1-pcie.c
> new file mode 100644
> index 0000000000000..75477bea7f700
> --- /dev/null
> +++ b/drivers/phy/phy-spacemit-k1-pcie.c
> @@ -0,0 +1,670 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SpacemiT K1 PCIe and PCIe/USB 3 combo PHY driver
> + *
> + * Copyright (C) 2025 by RISCstar Solutions Corporation.  All rights reserved.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +/*
> + * Three PCIe ports are supported in the SpacemiT K1 SoC, and this driver
> + * supports their PHYs.
> + *
> + * The PHY for PCIe port A is different from the PHYs for ports B and C:
> + * - It has one lane, while ports B and C have two
> + * - It is a combo PHY can be used for PCIe or USB 3
> + * - It can automatically calibrate PCIe TX and RX termination settings
> + *
> + * The PHY functionality for PCIe ports B and C is identical:
> + * - They have two PCIe lanes (but can be restricted to 1 via device tree)
> + * - They are used for PCIe only
> + * - They are configured using TX and RX values computed for port A
> + *
> + * A given board is designed to use the combo PHY for either PCIe or USB 3.
> + * Whether the combo PHY is configured for PCIe or USB 3 is specified in
> + * device tree using a phandle plus an argument.  The argument indicates
> + * the type (either PHY_TYPE_PCIE or PHY_TYPE_USB3).
> + *
> + * Each PHY has a reset that it gets and deasserts during initialization.
> + * Each depends also on other clocks and resets provided by the controller
> + * hardware (PCIe or USB) it is associated with.  The controller drivers
> + * are required to enable any clocks and de-assert any resets that affect
> + * PHY operation.  In addition each PHY implements an internal PLL, driven
> + * by an external (24 MHz) oscillator.
> + *
> + * PCIe PHYs must be programmed with RX and TX calibration values.  The
> + * combo PHY is the only one that can determine these values.  They are
> + * determined by temporarily enabling the combo PHY in PCIe mode at probe
> + * time (if necessary).  This calibration only needs to be done once, and
> + * when it has completed the TX and RX values are saved.
> + *
> + * To allow the combo PHY to be enabled for calibration, the resets and
> + * clocks it uses in PCIe mode must be supplied.
> + */
> +
> +struct k1_pcie_phy {
> +	struct device *dev;		/* PHY provider device */
> +	struct phy *phy;
> +	void __iomem *regs;
> +	u32 pcie_lanes;			/* Max (1 or 2) unless limited by DT */
> +	struct clk *pll;
> +	struct clk_hw pll_hw;		/* Private PLL clock */
> +
> +	/* The remaining fields are only used for the combo PHY */
> +	u32 type;			/* PHY_TYPE_PCIE or PHY_TYPE_USB3 */
> +	struct regmap *pmu;		/* MMIO regmap (no errors) */
> +};
> +
> +#define CALIBRATION_TIMEOUT		500000	/* For combo PHY (usec) */
> +#define PLL_TIMEOUT			500000	/* For PHY PLL lock (usec) */
> +#define POLL_DELAY			500	/* Time between polls (usec) */
> +
> +/* Selecting the combo PHY operating mode requires APMU regmap access */
> +#define SYSCON_APMU			"spacemit,apmu"
> +
> +/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY only) */
> +
> +#define PMUA_USB_PHY_CTRL0			0x0110
> +#define COMBO_PHY_SEL			BIT(3)	/* 0: PCIe; 1: USB 3 */
> +
> +#define PCIE_CLK_RES_CTRL			0x03cc
> +#define PCIE_APP_HOLD_PHY_RST		BIT(30)
> +
> +/* PHY register space */
> +
> +/* Offset between lane 0 and lane 1 registers when there are two */
> +#define PHY_LANE_OFFSET				0x0400
> +
> +/* PHY PLL configuration */
> +#define PCIE_PU_ADDR_CLK_CFG			0x0008
> +#define PLL_READY			BIT(0)		/* read-only */
> +#define CFG_INTERNAL_TIMER_ADJ		GENMASK(10, 7)
> +#define TIMER_ADJ_USB		0x2
> +#define TIMER_ADJ_PCIE		0x6
> +#define CFG_SW_PHY_INIT_DONE		BIT(11)	/* We set after PLL config */
> +
> +#define PCIE_RC_DONE_STATUS			0x0018
> +#define CFG_FORCE_RCV_RETRY		BIT(10)		/* Used for PCIe */
> +
> +/* PCIe PHY lane calibration; assumes 24MHz input clock */
> +#define PCIE_RC_CAL_REG2			0x0020
> +#define RC_CAL_TOGGLE			BIT(22)
> +#define CLKSEL				GENMASK(31, 29)
> +#define CLKSEL_24M		0x3
> +
> +/* Additional PHY PLL configuration (USB 3 and PCIe) */
> +#define PCIE_PU_PLL_1				0x0048
> +#define REF_100_WSSC			BIT(12)	/* 1: input is 100MHz, SSC */
> +#define FREF_SEL			GENMASK(15, 13)
> +#define FREF_24M		0x1
> +#define SSC_DEP_SEL			GENMASK(19, 16)
> +#define SSC_DEP_NONE		0x0
> +#define SSC_DEP_5000PPM		0xa
> +
> +/* PCIe PHY configuration */
> +#define PCIE_PU_PLL_2				0x004c
> +#define GEN_REF100			BIT(4)	/* 1: generate 100MHz clk */
> +
> +#define PCIE_RX_REG1				0x0050
> +#define EN_RTERM			BIT(3)
> +#define AFE_RTERM_REG			GENMASK(11, 8)
> +
> +#define PCIE_RX_REG2				0x0054
> +#define RX_RTERM_SEL			BIT(5)	/* 0: use AFE_RTERM_REG value */
> +
> +#define PCIE_LTSSM_DIS_ENTRY			0x005c
> +#define CFG_REFCLK_MODE			GENMASK(9, 8)
> +#define RFCLK_MODE_DRIVER	0x1
> +#define OVRD_REFCLK_MODE		BIT(10)	/* 1: use CFG_RFCLK_MODE */
> +
> +#define PCIE_TX_REG1				0x0064
> +#define TX_RTERM_REG			GENMASK(15, 12)
> +#define TX_RTERM_SEL			BIT(25)	/* 1: use TX_RTERM_REG */
> +
> +/* Zeroed for the combo PHY operating in USB mode */
> +#define USB3_TEST_CTRL				0x0068
> +
> +/* PHY calibration values, determined by the combo PHY at probe time */
> +#define PCIE_RCAL_RESULT			0x0084	/* Port A PHY only */
> +#define RTERM_VALUE_RX			GENMASK(3, 0)
> +#define RTERM_VALUE_TX			GENMASK(7, 4)
> +#define R_TUNE_DONE			BIT(10)
> +
> +static u32 k1_phy_rterm = ~0;     /* Invalid initial value */

This global variable would have deserved a comment explaining
why the value is global, instead the reason is only present in the
commit message....

> +
> +/* Save the RX and TX receiver termination values */
> +static void k1_phy_rterm_set(u32 val)
> +{
> +	k1_phy_rterm = val & (RTERM_VALUE_RX | RTERM_VALUE_TX);
> +}
> +
> +static bool k1_phy_rterm_valid(void)
> +{
> +	/* Valid if no bits outside those we care about are set */
> +	return !(k1_phy_rterm & ~(RTERM_VALUE_RX | RTERM_VALUE_TX));
> +}
> +
> +static u32 k1_phy_rterm_rx(void)
> +{
> +	return FIELD_GET(RTERM_VALUE_RX, k1_phy_rterm);
> +}
> +
> +static u32 k1_phy_rterm_tx(void)
> +{
> +	return FIELD_GET(RTERM_VALUE_TX, k1_phy_rterm);
> +}
> +
> +/* Only the combo PHY has a PMU pointer defined */
> +static bool k1_phy_port_a(struct k1_pcie_phy *k1_phy)
> +{
> +	return !!k1_phy->pmu;
> +}
> +
> +/* The PLL clocks are driven by the external oscillator */
> +static const struct clk_parent_data k1_pcie_phy_data[] = {
> +	{ .fw_name = "refclk", },
> +};
> +
> +static struct k1_pcie_phy *clk_hw_to_k1_phy(struct clk_hw *clk_hw)
> +{
> +	return container_of(clk_hw, struct k1_pcie_phy, pll_hw);
> +}
> +
> +/* USB mode only works on the combo PHY, which has only one lane */
> +static void k1_pcie_phy_pll_prepare_usb(struct k1_pcie_phy *k1_phy)
> +{
> +	void __iomem *regs = k1_phy->regs;
> +	u32 val;
> +
> +	val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
> +	val &= ~CFG_INTERNAL_TIMER_ADJ;
> +	val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_USB);
> +	writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
> +
> +	val = readl(regs + PCIE_PU_PLL_1);
> +	val &= ~SSC_DEP_SEL;
> +	val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_5000PPM);
> +	writel(val, regs + PCIE_PU_PLL_1);
> +}
> +
> +/* Perform PCIe-specific register updates before starting the PLL clock */
> +static void k1_pcie_phy_pll_prepare_pcie(struct k1_pcie_phy *k1_phy)
> +{
> +	void __iomem *regs = k1_phy->regs;
> +	u32 val;
> +	u32 i;
> +
> +	for (i = 0; i < k1_phy->pcie_lanes; i++) {
> +		val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
> +		val &= ~CFG_INTERNAL_TIMER_ADJ;
> +		val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_PCIE);
> +		writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
> +
> +		regs += PHY_LANE_OFFSET;	/* Next lane */
> +	}
> +
> +	regs = k1_phy->regs;
> +	val = readl(regs + PCIE_RC_DONE_STATUS);
> +	val |= CFG_FORCE_RCV_RETRY;
> +	writel(val, regs + PCIE_RC_DONE_STATUS);
> +
> +	val = readl(regs + PCIE_PU_PLL_1);
> +	val &= ~SSC_DEP_SEL;
> +	val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_NONE);
> +	writel(val, regs + PCIE_PU_PLL_1);
> +
> +	val = readl(regs + PCIE_PU_PLL_2);
> +	val |= GEN_REF100;		/* Enable 100 MHz PLL output clock */
> +	writel(val, regs + PCIE_PU_PLL_2);
> +}
> +
> +static int k1_pcie_phy_pll_prepare(struct clk_hw *clk_hw)
> +{
> +	struct k1_pcie_phy *k1_phy = clk_hw_to_k1_phy(clk_hw);
> +	void __iomem *regs = k1_phy->regs;
> +	u32 val;
> +	u32 i;
> +
> +	if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3)
> +		k1_pcie_phy_pll_prepare_usb(k1_phy);
> +	else
> +		k1_pcie_phy_pll_prepare_pcie(k1_phy);
> +
> +	/*
> +	 * Disable 100 MHz input reference with spread-spectrum
> +	 * clocking and select the 24 MHz clock input frequency
> +	 */
> +	val = readl(regs + PCIE_PU_PLL_1);
> +	val &= ~REF_100_WSSC;
> +	val &= ~FREF_SEL;
> +	val |= FIELD_PREP(FREF_SEL, FREF_24M);
> +	writel(val, regs + PCIE_PU_PLL_1);
> +
> +	/* Mark PLL configuration done on all lanes */
> +	for (i = 0; i < k1_phy->pcie_lanes; i++) {
> +		val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
> +		val |= CFG_SW_PHY_INIT_DONE;
> +		writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
> +
> +		regs += PHY_LANE_OFFSET;	/* Next lane */
> +	}
> +
> +	/*
> +	 * Wait for indication the PHY PLL is locked.  Lanes for ports
> +	 * B and C share a PLL, so it's enough to sample just lane 0.
> +	 */
> +	return readl_poll_timeout(k1_phy->regs + PCIE_PU_ADDR_CLK_CFG,
> +				  val, val & PLL_READY,
> +				  POLL_DELAY, PLL_TIMEOUT);
> +}
> +
> +/* Prepare implies enable, and once enabled, it's always on */
> +static const struct clk_ops k1_pcie_phy_pll_ops = {
> +	.prepare	= k1_pcie_phy_pll_prepare,
> +};
> +
> +/* We represent the PHY PLL as a private clock */
> +static int k1_pcie_phy_pll_setup(struct k1_pcie_phy *k1_phy)
> +{
> +	struct clk_hw *hw = &k1_phy->pll_hw;
> +	struct device *dev = k1_phy->dev;
> +	struct clk_init_data init = { };
> +	char *name;
> +	int ret;
> +
> +	name = kasprintf(GFP_KERNEL, "pcie%u_phy_pll", k1_phy->phy->id);
> +	if (!name)
> +		return -ENOMEM;
> +
> +	init.name = name;
> +	init.ops = &k1_pcie_phy_pll_ops;
> +	init.parent_data = k1_pcie_phy_data;
> +	init.num_parents = ARRAY_SIZE(k1_pcie_phy_data);
> +
> +	hw->init = &init;
> +
> +	ret = devm_clk_hw_register(dev, hw);
> +
> +	kfree(name);	/* __clk_register() duplicates the name we provide */
> +
> +	if (ret)
> +		return ret;
> +
> +	k1_phy->pll = devm_clk_hw_get_clk(dev, hw, "pll");
> +	if (IS_ERR(k1_phy->pll))
> +		return PTR_ERR(k1_phy->pll);
> +
> +	return 0;
> +}
> +
> +/* Select PCIe or USB 3 mode for the combo PHY. */
> +static void k1_combo_phy_sel(struct k1_pcie_phy *k1_phy, bool usb)
> +{
> +	struct regmap *pmu = k1_phy->pmu;
> +
> +	/* Only change it if it's not already in the desired state */
> +	if (!regmap_test_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL) == usb)
> +		regmap_assign_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL, usb);
> +}
> +
> +static void k1_pcie_phy_init_pcie(struct k1_pcie_phy *k1_phy)
> +{
> +	u32 rx_rterm = k1_phy_rterm_rx();
> +	u32 tx_rterm = k1_phy_rterm_tx();
> +	void __iomem *regs;
> +	u32 val;
> +	int i;
> +
> +	/* For the combo PHY, set PHY to PCIe mode */
> +	if (k1_phy_port_a(k1_phy))
> +		k1_combo_phy_sel(k1_phy, false);
> +
> +	regs = k1_phy->regs;
> +	for (i = 0; i < k1_phy->pcie_lanes; i++) {
> +		val = readl(regs + PCIE_RX_REG1);
> +
> +		/* Set RX analog front-end receiver termination value */
> +		val &= ~AFE_RTERM_REG;
> +		val |= FIELD_PREP(AFE_RTERM_REG, rx_rterm);
> +
> +		/* And enable refclock receiver termination */
> +		val |= EN_RTERM;
> +		writel(val, regs + PCIE_RX_REG1);
> +
> +		val = readl(regs + PCIE_RX_REG2);
> +		/* Use PCIE_RX_REG1 AFE_RTERM_REG value */
> +		val &= ~RX_RTERM_SEL;
> +		writel(val, regs + PCIE_RX_REG2);
> +
> +		val = readl(regs + PCIE_TX_REG1);
> +
> +		/* Set TX driver termination value */
> +		val &= ~TX_RTERM_REG;
> +		val |= FIELD_PREP(TX_RTERM_REG, tx_rterm);
> +
> +		/* Use PCIE_TX_REG1 TX_RTERM_REG value */
> +		val |= TX_RTERM_SEL;
> +		writel(val, regs + PCIE_TX_REG1);
> +
> +		/* Set the input clock to 24 MHz, and clear RC_CAL_TOGGLE */
> +		val = readl(regs + PCIE_RC_CAL_REG2);
> +		val &= CLKSEL;
> +		val |= FIELD_PREP(CLKSEL, CLKSEL_24M);
> +		val &= ~RC_CAL_TOGGLE;
> +		writel(val, regs + PCIE_RC_CAL_REG2);
> +
> +		/* Now trigger recalibration by setting RC_CAL_TOGGLE again */
> +		val |= RC_CAL_TOGGLE;
> +		writel(val, regs + PCIE_RC_CAL_REG2);
> +
> +		val = readl(regs + PCIE_LTSSM_DIS_ENTRY);
> +		/* Override the reference clock; set to refclk driver mode */
> +		val |= OVRD_REFCLK_MODE;
> +		val &= ~CFG_REFCLK_MODE;
> +		val |= FIELD_PREP(CFG_REFCLK_MODE, RFCLK_MODE_DRIVER);
> +		writel(val, regs + PCIE_LTSSM_DIS_ENTRY);
> +
> +		regs += PHY_LANE_OFFSET;	/* Next lane */
> +	}
> +}
> +
> +/* Only called for combo PHY */
> +static void k1_pcie_phy_init_usb(struct k1_pcie_phy *k1_phy)
> +{
> +	k1_combo_phy_sel(k1_phy, true);
> +
> +	/* We're not doing any testing */
> +	writel(0, k1_phy->regs + USB3_TEST_CTRL);
> +}
> +
> +static int k1_pcie_phy_init(struct phy *phy)
> +{
> +	struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy);
> +
> +	/* Note: port type is only valid for port A (both checks needed) */
> +	if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3)
> +		k1_pcie_phy_init_usb(k1_phy);
> +	else
> +		k1_pcie_phy_init_pcie(k1_phy);
> +
> +
> +	return clk_prepare_enable(k1_phy->pll);
> +}
> +
> +static int k1_pcie_phy_exit(struct phy *phy)
> +{
> +	struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy);
> +
> +	clk_disable_unprepare(k1_phy->pll);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops k1_pcie_phy_ops = {
> +	.init		= k1_pcie_phy_init,
> +	.exit		= k1_pcie_phy_exit,
> +	.owner		= THIS_MODULE,
> +};
> +
> +/*
> + * Get values needed for calibrating PHYs operating in PCIe mode.  Only
> + * the combo PHY is able to do this, and its calibration values are used
> + * for configuring all PCIe PHYs.
> + *
> + * We always need to de-assert the "global" reset on the combo PHY,
> + * because the USB driver depends on it.  If used for PCIe, that driver
> + * will (also) de-assert this, but by leaving it de-asserted for the
> + * combo PHY, the USB driver doesn't have to do this.  Note: although
> + * SpacemiT refers to this as the global reset, we name the "phy" reset.
> + *
> + * In addition, we guarantee the APP_HOLD_PHY_RESET bit is clear for the
> + * combo PHY, so the USB driver doesn't have to manage that either.  The
> + * PCIe driver is free to change this bit for normal operation.
> + *
> + * Calibration only needs to be done once.  It's possible calibration has
> + * already completed (e.g., it might have happened in the boot loader, or
> + * -EPROBE_DEFER might result in this function being called again).  So we
> + * check that early too, to avoid doing it more than once.
> + *
> + * Otherwise we temporarily power up the PHY using the PCIe app clocks
> + * and resets, wait for the hardware to indicate calibration is done,
> + * grab the value, then shut the PHY down again.
> + */
> +static int k1_pcie_combo_phy_calibrate(struct k1_pcie_phy *k1_phy)
> +{
> +	struct reset_control_bulk_data resets[] = {
> +		{ .id = "dbi", },
> +		{ .id = "mstr", },
> +		{ .id = "slv", },
> +	};
> +	struct clk_bulk_data clocks[] = {
> +		{ .id = "dbi", },
> +		{ .id = "mstr", },
> +		{ .id = "slv", },
> +	};
> +	struct device *dev = k1_phy->dev;
> +	int ret = 0;
> +	int val;
> +
> +	/* Nothing to do if we already set the receiver termination value */
> +	if (k1_phy_rterm_valid())
> +		return 0;
> +
> +	/*
> +	 * We also guarantee the APP_HOLD_PHY_RESET bit is clear.  We can
> +	 * leave this bit clear even if an error happens below.
> +	 */
> +	regmap_assign_bits(k1_phy->pmu, PCIE_CLK_RES_CTRL,
> +			   PCIE_APP_HOLD_PHY_RST, false);
> +
> +	/* If the calibration already completed (e.g. by U-Boot), we're done */
> +	val = readl(k1_phy->regs + PCIE_RCAL_RESULT);
> +	if (val & R_TUNE_DONE)
> +		goto out_tune_done;
> +
> +	/* Put the PHY into PCIe mode */
> +	k1_combo_phy_sel(k1_phy, false);
> +
> +	/* Get and enable the PCIe app clocks */
> +	ret = clk_bulk_get(dev, ARRAY_SIZE(clocks), clocks);
> +	if (ret < 0)
> +		goto out_tune_done;
> +	ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
> +	if (ret)
> +		goto out_put_clocks;
> +
> +	/* Get the PCIe application resets (not the PHY reset) */
> +	ret = reset_control_bulk_get_shared(dev, ARRAY_SIZE(resets), resets);
> +	if (ret)
> +		goto out_disable_clocks;
> +
> +	/* De-assert the PCIe application resets */
> +	ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets);
> +	if (ret)
> +		goto out_put_resets;
> +
> +	/*
> +	 * This is the core activity here.  Wait for the hardware to
> +	 * signal that it has completed calibration/tuning.  Once it
> +	 * has, the register value will contain the values we'll
> +	 * use to configure PCIe PHYs.
> +	 */
> +	ret = readl_poll_timeout(k1_phy->regs + PCIE_RCAL_RESULT,
> +				 val, val & R_TUNE_DONE,
> +				 POLL_DELAY, CALIBRATION_TIMEOUT);
> +
> +	/* Clean up.  We're done with the resets and clocks */
> +	reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
> +out_put_resets:
> +	reset_control_bulk_put(ARRAY_SIZE(resets), resets);
> +out_disable_clocks:
> +	clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
> +out_put_clocks:
> +	clk_bulk_put(ARRAY_SIZE(clocks), clocks);
> +out_tune_done:
> +	/* If we got the value without timing out, set k1_phy_rterm */
> +	if (!ret)
> +		k1_phy_rterm_set(val);
> +
> +	return ret;
> +}
> +
> +static struct phy *
> +k1_pcie_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args)
> +{
> +	struct k1_pcie_phy *k1_phy = dev_get_drvdata(dev);
> +	u32 type;
> +
> +	/* The argument specifying the PHY mode is required */
> +	if (args->args_count != 1)
> +		return ERR_PTR(-EINVAL);
> +
> +	/* We only support PCIe and USB 3 mode */
> +	type = args->args[0];
> +	if (type != PHY_TYPE_PCIE && type != PHY_TYPE_USB3)
> +		return ERR_PTR(-EINVAL);
> +
> +	/* This PHY can only be used once */
> +	if (k1_phy->type != PHY_NONE)
> +		return ERR_PTR(-EBUSY);
> +
> +	k1_phy->type = type;
> +
> +	return k1_phy->phy;
> +}
> +
> +/* Use the maximum number of PCIe lanes unless limited by device tree */
> +static u32 k1_pcie_num_lanes(struct k1_pcie_phy *k1_phy, bool port_a)
> +{
> +	struct device *dev = k1_phy->dev;
> +	u32 count = 0;
> +	u32 max;
> +	int ret;
> +
> +	ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &count);
> +	if (count == 1)
> +		return 1;
> +
> +	if (count == 2 && !port_a)
> +		return 2;
> +
> +	max = port_a ? 1 : 2;
> +	if (ret != -EINVAL)
> +		dev_warn(dev, "bad lane count %u for port; using %u\n",
> +			 count, max);
> +
> +	return max;
> +}
> +
> +static int k1_pcie_combo_phy_probe(struct k1_pcie_phy *k1_phy)
> +{
> +	struct device *dev = k1_phy->dev;
> +	struct regmap *regmap;
> +	int ret;
> +
> +	/* Setting the PHY mode requires access to the PMU regmap */
> +	regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), SYSCON_APMU);
> +	if (IS_ERR(regmap))
> +		return dev_err_probe(dev, PTR_ERR(regmap), "failed to get PMU\n");
> +	k1_phy->pmu = regmap;
> +
> +	ret = k1_pcie_combo_phy_calibrate(k1_phy);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "calibration failed\n");
> +
> +	/* Needed by k1_pcie_combo_phy_xlate(), which also sets k1_phy->type */
> +	dev_set_drvdata(dev, k1_phy);
> +
> +	return 0;
> +}
> +
> +static int k1_pcie_phy_probe(struct platform_device *pdev)
> +{
> +	struct phy *(*xlate)(struct device *dev,
> +			     const struct of_phandle_args *args);
> +	struct device *dev = &pdev->dev;
> +	struct reset_control *phy_reset;
> +	struct phy_provider *provider;
> +	struct k1_pcie_phy *k1_phy;
> +	bool probing_port_a;
> +	int ret;
> +
> +	xlate = of_device_get_match_data(dev);
> +	probing_port_a = xlate == k1_pcie_combo_phy_xlate;
> +
> +	/* Only the combo PHY can calibrate, so it must probe first */
> +	if (!k1_phy_rterm_valid() && !probing_port_a)
> +		return -EPROBE_DEFER;
> +
> +	k1_phy = devm_kzalloc(dev, sizeof(*k1_phy), GFP_KERNEL);
> +	if (!k1_phy)
> +		return -ENOMEM;
> +	k1_phy->dev = dev;
> +
> +	k1_phy->regs = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(k1_phy->regs))
> +		return dev_err_probe(dev, PTR_ERR(k1_phy->regs),
> +				     "error mapping registers\n");
> +
> +	/* De-assert the PHY (global) reset and leave it that way */
> +	phy_reset = devm_reset_control_get_exclusive_deasserted(dev, "phy");
> +	if (IS_ERR(phy_reset))
> +		return PTR_ERR(phy_reset);
> +
> +	if (probing_port_a) {
> +		ret = k1_pcie_combo_phy_probe(k1_phy);
> +		if (ret)
> +			return dev_err_probe(dev, ret,
> +					     "error probing combo phy\n");
> +	}
> +
> +	k1_phy->pcie_lanes = k1_pcie_num_lanes(k1_phy, probing_port_a);
> +
> +	k1_phy->phy = devm_phy_create(dev, NULL, &k1_pcie_phy_ops);
> +	if (IS_ERR(k1_phy->phy))
> +		return dev_err_probe(dev, PTR_ERR(k1_phy->phy),
> +				     "error creating phy\n");
> +	phy_set_drvdata(k1_phy->phy, k1_phy);
> +
> +	ret = k1_pcie_phy_pll_setup(k1_phy);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "error initializing clock\n");
> +
> +	provider = devm_of_phy_provider_register(dev, xlate);
> +	if (IS_ERR(provider))
> +		return dev_err_probe(dev, PTR_ERR(provider),
> +				     "error registering provider\n");
> +	return 0;
> +}
> +
> +static const struct of_device_id k1_pcie_phy_of_match[] = {
> +	{ .compatible = "spacemit,k1-combo-phy", k1_pcie_combo_phy_xlate, },
> +	{ .compatible = "spacemit,k1-pcie-phy", of_phy_simple_xlate, },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, k1_pcie_phy_of_match);
> +
> +static struct platform_driver k1_pcie_phy_driver = {
> +	.probe	= k1_pcie_phy_probe,
> +	.driver = {
> +		.of_match_table	= k1_pcie_phy_of_match,
> +		.name = "spacemit-k1-pcie-phy",
> +	}
> +};
> +module_platform_driver(k1_pcie_phy_driver);
> +
> +MODULE_DESCRIPTION("SpacemiT K1 PCIe and USB 3 PHY driver");
> +MODULE_LICENSE("GPL");

The code is quite hard to read, with pleny of useless comments
when the actual comments we needs are either in the wrong place
or just missing.

Anyway, no big comment on the code or the API usage, all looks good:

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks,
Neil


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Re: [PATCH v6 4/7] phy: spacemit: Introduce PCIe/combo PHY

[Alex Elder]

On 11/18/25 2:56 AM, Neil Armstrong wrote:
> On 11/13/25 22:45, Alex Elder wrote:
>> Introduce a driver that supports three PHYs found on the SpacemiT
>> K1 SoC.  The first PHY is a combo PHY that can be configured for
>> use for either USB 3 or PCIe.  The other two PHYs support PCIe
>> only.
>>
>> All three PHYs must be programmed with an 8 bit receiver termination
>> value, which must be determined dynamically.  Only the combo PHY is
>> able to determine this value.  The combo PHY performs a special
>> calibration step at probe time to discover this, and that value is
>> used to program each PHY that operates in PCIe mode.  The combo
>> PHY must therefore be probed before either of the PCIe-only PHYs
>> will be used.
>>
>> Each PHY has an internal PLL driven from an external oscillator.
>> This PLL started when the PHY is first initialized, and stays
>> on thereafter.
>>
>> During normal operation, the USB or PCIe driver using the PHY must
>> ensure (other) clocks and resets are set up properly.
>>
>> However PCIe mode clocks are enabled and resets are de-asserted
>> temporarily by this driver to perform the calibration step on the
>> combo PHY.
>>
>> Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
>> Signed-off-by: Alex Elder <elder@riscstar.com>
>> ---

. . .

>> diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/phy- 
>> spacemit-k1-pcie.c
>> new file mode 100644
>> index 0000000000000..75477bea7f700
>> --- /dev/null
>> +++ b/drivers/phy/phy-spacemit-k1-pcie.c
>> @@ -0,0 +1,670 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * SpacemiT K1 PCIe and PCIe/USB 3 combo PHY driver
>> + *
>> + * Copyright (C) 2025 by RISCstar Solutions Corporation.  All rights 
>> reserved.
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/kernel.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/reset.h>
>> +
>> +#include <dt-bindings/phy/phy.h>
>> +
>> +/*
>> + * Three PCIe ports are supported in the SpacemiT K1 SoC, and this 
>> driver
>> + * supports their PHYs.
>> + *
>> + * The PHY for PCIe port A is different from the PHYs for ports B and C:
>> + * - It has one lane, while ports B and C have two
>> + * - It is a combo PHY can be used for PCIe or USB 3
>> + * - It can automatically calibrate PCIe TX and RX termination settings
>> + *
>> + * The PHY functionality for PCIe ports B and C is identical:
>> + * - They have two PCIe lanes (but can be restricted to 1 via device 
>> tree)
>> + * - They are used for PCIe only
>> + * - They are configured using TX and RX values computed for port A
>> + *
>> + * A given board is designed to use the combo PHY for either PCIe or 
>> USB 3.
>> + * Whether the combo PHY is configured for PCIe or USB 3 is specified in
>> + * device tree using a phandle plus an argument.  The argument indicates
>> + * the type (either PHY_TYPE_PCIE or PHY_TYPE_USB3).
>> + *
>> + * Each PHY has a reset that it gets and deasserts during 
>> initialization.
>> + * Each depends also on other clocks and resets provided by the 
>> controller
>> + * hardware (PCIe or USB) it is associated with.  The controller drivers
>> + * are required to enable any clocks and de-assert any resets that 
>> affect
>> + * PHY operation.  In addition each PHY implements an internal PLL, 
>> driven
>> + * by an external (24 MHz) oscillator.
>> + *
>> + * PCIe PHYs must be programmed with RX and TX calibration values.  The
>> + * combo PHY is the only one that can determine these values.  They are
>> + * determined by temporarily enabling the combo PHY in PCIe mode at 
>> probe
>> + * time (if necessary).  This calibration only needs to be done once, 
>> and
>> + * when it has completed the TX and RX values are saved.
>> + *
>> + * To allow the combo PHY to be enabled for calibration, the resets and
>> + * clocks it uses in PCIe mode must be supplied.
>> + */
>> +
>> +struct k1_pcie_phy {
>> +    struct device *dev;        /* PHY provider device */
>> +    struct phy *phy;
>> +    void __iomem *regs;
>> +    u32 pcie_lanes;            /* Max (1 or 2) unless limited by DT */
>> +    struct clk *pll;
>> +    struct clk_hw pll_hw;        /* Private PLL clock */
>> +
>> +    /* The remaining fields are only used for the combo PHY */
>> +    u32 type;            /* PHY_TYPE_PCIE or PHY_TYPE_USB3 */
>> +    struct regmap *pmu;        /* MMIO regmap (no errors) */
>> +};
>> +
>> +#define CALIBRATION_TIMEOUT        500000    /* For combo PHY (usec) */
>> +#define PLL_TIMEOUT            500000    /* For PHY PLL lock (usec) */
>> +#define POLL_DELAY            500    /* Time between polls (usec) */
>> +
>> +/* Selecting the combo PHY operating mode requires APMU regmap access */
>> +#define SYSCON_APMU            "spacemit,apmu"
>> +
>> +/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY 
>> only) */
>> +
>> +#define PMUA_USB_PHY_CTRL0            0x0110
>> +#define COMBO_PHY_SEL            BIT(3)    /* 0: PCIe; 1: USB 3 */
>> +
>> +#define PCIE_CLK_RES_CTRL            0x03cc
>> +#define PCIE_APP_HOLD_PHY_RST        BIT(30)
>> +
>> +/* PHY register space */
>> +
>> +/* Offset between lane 0 and lane 1 registers when there are two */
>> +#define PHY_LANE_OFFSET                0x0400
>> +
>> +/* PHY PLL configuration */
>> +#define PCIE_PU_ADDR_CLK_CFG            0x0008
>> +#define PLL_READY            BIT(0)        /* read-only */
>> +#define CFG_INTERNAL_TIMER_ADJ        GENMASK(10, 7)
>> +#define TIMER_ADJ_USB        0x2
>> +#define TIMER_ADJ_PCIE        0x6
>> +#define CFG_SW_PHY_INIT_DONE        BIT(11)    /* We set after PLL 
>> config */
>> +
>> +#define PCIE_RC_DONE_STATUS            0x0018
>> +#define CFG_FORCE_RCV_RETRY        BIT(10)        /* Used for PCIe */
>> +
>> +/* PCIe PHY lane calibration; assumes 24MHz input clock */
>> +#define PCIE_RC_CAL_REG2            0x0020
>> +#define RC_CAL_TOGGLE            BIT(22)
>> +#define CLKSEL                GENMASK(31, 29)
>> +#define CLKSEL_24M        0x3
>> +
>> +/* Additional PHY PLL configuration (USB 3 and PCIe) */
>> +#define PCIE_PU_PLL_1                0x0048
>> +#define REF_100_WSSC            BIT(12)    /* 1: input is 100MHz, SSC */
>> +#define FREF_SEL            GENMASK(15, 13)
>> +#define FREF_24M        0x1
>> +#define SSC_DEP_SEL            GENMASK(19, 16)
>> +#define SSC_DEP_NONE        0x0
>> +#define SSC_DEP_5000PPM        0xa
>> +
>> +/* PCIe PHY configuration */
>> +#define PCIE_PU_PLL_2                0x004c
>> +#define GEN_REF100            BIT(4)    /* 1: generate 100MHz clk */
>> +
>> +#define PCIE_RX_REG1                0x0050
>> +#define EN_RTERM            BIT(3)
>> +#define AFE_RTERM_REG            GENMASK(11, 8)
>> +
>> +#define PCIE_RX_REG2                0x0054
>> +#define RX_RTERM_SEL            BIT(5)    /* 0: use AFE_RTERM_REG 
>> value */
>> +
>> +#define PCIE_LTSSM_DIS_ENTRY            0x005c
>> +#define CFG_REFCLK_MODE            GENMASK(9, 8)
>> +#define RFCLK_MODE_DRIVER    0x1
>> +#define OVRD_REFCLK_MODE        BIT(10)    /* 1: use CFG_RFCLK_MODE */
>> +
>> +#define PCIE_TX_REG1                0x0064
>> +#define TX_RTERM_REG            GENMASK(15, 12)
>> +#define TX_RTERM_SEL            BIT(25)    /* 1: use TX_RTERM_REG */
>> +
>> +/* Zeroed for the combo PHY operating in USB mode */
>> +#define USB3_TEST_CTRL                0x0068
>> +
>> +/* PHY calibration values, determined by the combo PHY at probe time */
>> +#define PCIE_RCAL_RESULT            0x0084    /* Port A PHY only */
>> +#define RTERM_VALUE_RX            GENMASK(3, 0)
>> +#define RTERM_VALUE_TX            GENMASK(7, 4)
>> +#define R_TUNE_DONE            BIT(10)
>> +
>> +static u32 k1_phy_rterm = ~0;     /* Invalid initial value */
> 
> This global variable would have deserved a comment explaining
> why the value is global, instead the reason is only present in the
> commit message....

The (somewhat strange) overall scheme is described in a comment
block at the top of the file.  But I think you're right, a short
comment could at least refer back to that, and say "this is
where the calibration value is held" or something.

>> +/* Save the RX and TX receiver termination values */
>> +static void k1_phy_rterm_set(u32 val)
>> +{
>> +    k1_phy_rterm = val & (RTERM_VALUE_RX | RTERM_VALUE_TX);
>> +}
>> +
>> +static bool k1_phy_rterm_valid(void)
>> +{
>> +    /* Valid if no bits outside those we care about are set */
>> +    return !(k1_phy_rterm & ~(RTERM_VALUE_RX | RTERM_VALUE_TX));
>> +}

. . .

>> +module_platform_driver(k1_pcie_phy_driver);
>> +
>> +MODULE_DESCRIPTION("SpacemiT K1 PCIe and USB 3 PHY driver");
>> +MODULE_LICENSE("GPL");
> 
> The code is quite hard to read, with pleny of useless comments
> when the actual comments we needs are either in the wrong place
> or just missing.

I think the way this calibration works is unusual and a bit
confusing, and I might have gone too far trying to explain it.

It would be more helpful for you to provide examples of what
comments you think are useless, and where there are things that
would benefit from better explanation (as you did for the lack
of a comment for the k1_phy_rterm value).  I want very much to
make things better, but your statement offers no guidance on
what you're looking for.

> Anyway, no big comment on the code or the API usage, all looks good:
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thank you very much for reviewing this Neil.

					-Alex

> Thanks,
> Neil
> 


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