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([2a01:e0a:3d9:2080:fef9:cf1c:18f:2ab8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4efe6d0dbsm21967626f8f.40.2025.06.04.11.16.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Jun 2025 11:16:37 -0700 (PDT) Message-ID: Date: Wed, 4 Jun 2025 20:16:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Subject: Re: [PATCH v1 1/2] PCI: qcom: Add equalization settings for 8.0 GT/s To: Ziyue Zhang , lpieralisi@kernel.org, kwilczynski@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, abel.vesa@linaro.org, kw@linux.com, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_qianyu@quicinc.com, Qiang Yu References: <20250604091946.1890602-1-quic_ziyuzhan@quicinc.com> <20250604091946.1890602-2-quic_ziyuzhan@quicinc.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250604091946.1890602-2-quic_ziyuzhan@quicinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250604_111639_858302_B1869DC9 X-CRM114-Status: GOOD ( 18.45 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Neil Armstrong Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi, On 04/06/2025 11:19, Ziyue Zhang wrote: > Adding lane equalization setting for 8.0 GT/s to enhance link stability > and fix AER correctable errors reported on some platforms (eg. SA8775P). > > GEN3 and GEN4 require the same equalization setting. This setting is > programmed into a group of shadow registers, which can be switched to > configure equalization for different GEN speeds by writing 00b, 01b > to `RATE_SHADOW_SEL`. > > Hence program equalization registers in a loop using link speed as index, > so that equalization setting can be programmed for both GEN3 and GEN4. > > Co-developed-by: Qiang Yu > Signed-off-by: Qiang Yu > Signed-off-by: Ziyue Zhang > --- > drivers/pci/controller/dwc/pcie-designware.h | 1 - > drivers/pci/controller/dwc/pcie-qcom-common.c | 55 ++++++++++--------- > drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +- > drivers/pci/controller/dwc/pcie-qcom.c | 3 +- > 4 files changed, 32 insertions(+), 29 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index ce9e18554e42..388306991467 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -127,7 +127,6 @@ > #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) > #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 > #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) > -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1 > > #define GEN3_EQ_CONTROL_OFF 0x8A8 > #define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0) > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c > index 3aad19b56da8..48040f20b29c 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-common.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c > @@ -8,43 +8,46 @@ > #include "pcie-designware.h" > #include "pcie-qcom-common.h" > > -void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) > +void qcom_pcie_common_set_equalization(struct dw_pcie *pci) > { > u32 reg; > + u16 i; > > /* > * GEN3_RELATED_OFF register is repurposed to apply equalization > - * settings at various data transmission rates through registers namely > - * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF > + @@ -19,32 +21,34 @@ void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) > * determines the data rate for which these equalization settings are > * applied. > */ > - reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > - reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > - reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; > - reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, > - GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); > - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); > + for (i = PCIE_SPEED_8_0GT; i <= (pcie_link_speed[pci->max_link_speed] < PCIE_SPEED_32_0GT ? > + pcie_link_speed[pci->max_link_speed] : PCIE_SPEED_16_0GT); i++) { This is pretty hard to read, please simplify like: u16 speed, max_speed = PCIE_SPEED_16_0GT; if (pcie_link_speed[pci->max_link_speed] < PCIE_SPEED_32_0GT) max_speed = pcie_link_speed[pci->max_link_speed]; for (speed = PCIE_SPEED_8_0GT; speed < max_speedl; ++speed) { blah; } > + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; > + reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, > + i - PCIE_SPEED_8_0GT); > + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); > > - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); > - reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | > - GEN3_EQ_FMDC_N_EVALS | > - GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | > - GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); > - reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | > - FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | > - FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | > - FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); > - dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); > + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); > + reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | > + GEN3_EQ_FMDC_N_EVALS | > + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | > + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); > + reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | > + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | > + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | > + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); > + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); > > - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); > - reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | > - GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | > - GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | > - GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); > - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); > + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); > + reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | > + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | > + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | > + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); > + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); > + } > } > -EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); > +EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization); > > void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) > { > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h > index 7d88d29e4766..7f5ca2fd9a72 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-common.h > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h > @@ -8,7 +8,7 @@ > > struct dw_pcie; > > -void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci); > +void qcom_pcie_common_set_equalization(struct dw_pcie *pci); > void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci); > > #endif > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index c789e3f85655..51eac2dc6222 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -298,8 +298,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) > { > struct qcom_pcie *pcie = to_qcom_pcie(pci); > > + qcom_pcie_common_set_equalization(pci); > + > if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { > - qcom_pcie_common_set_16gt_equalization(pci); > qcom_pcie_common_set_16gt_lane_margining(pci); > } > Thanks, Neil -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy