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charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 8/30/2024 2:29 PM, Manivannan Sadhasivam wrote: > On Tue, Aug 27, 2024 at 10:27:56AM +0530, Sricharan R wrote: >> From: Nitheesh Sekar >> >> Add phy and controller nodes for a 2-lane Gen2 and >> 1-lane Gen2 PCIe buses. >> >> Signed-off-by: Nitheesh Sekar >> Signed-off-by: Sricharan R >> --- >> [v2] Removed relocatable flags, removed assigned-clock-rates, >> fixed rest of the cosmetic comments. >> >> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 168 +++++++++++++++++++++++++- >> 1 file changed, 166 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> index 7e6e2c121979..dd5d6b7ff094 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> @@ -9,6 +9,7 @@ >> #include >> #include >> #include >> +#include >> >> / { >> interrupt-parent = <&intc>; >> @@ -143,7 +144,33 @@ usbphy0: phy@5b000 { >> resets = <&gcc GCC_QUSB2_0_PHY_BCR>; >> >> #phy-cells = <0>; >> + }; >> + >> + pcie_x1phy: phy@7e000{ >> + compatible = "qcom,ipq5018-uniphy-pcie-gen2x1"; >> + reg = <0x0007e000 0x800>; >> + #phy-cells = <0>; >> + #clock-cells = <0>; >> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; >> + clock-names = "pipe"; >> + assigned-clocks = <&gcc GCC_PCIE1_PIPE_CLK>; >> + resets = <&gcc GCC_PCIE1_PHY_BCR>, >> + <&gcc GCC_PCIE1PHY_PHY_BCR>; >> + reset-names = "phy", "common"; >> + status = "disabled"; >> + }; >> >> + pcie_x2phy: phy@86000{ >> + compatible = "qcom,ipq5018-uniphy-pcie-gen2x2"; >> + reg = <0x00086000 0x1000>; >> + #phy-cells = <0>; >> + #clock-cells = <0>; >> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; >> + clock-names = "pipe"; >> + assigned-clocks = <&gcc GCC_PCIE0_PIPE_CLK>; >> + resets = <&gcc GCC_PCIE0_PHY_BCR>, >> + <&gcc GCC_PCIE0PHY_PHY_BCR>; >> + reset-names = "phy", "common"; >> status = "disabled"; >> }; >> >> @@ -170,8 +197,8 @@ gcc: clock-controller@1800000 { >> reg = <0x01800000 0x80000>; >> clocks = <&xo_board_clk>, >> <&sleep_clk>, >> - <0>, >> - <0>, >> + <&pcie_x2phy>, >> + <&pcie_x1phy>, >> <0>, >> <0>, >> <0>, >> @@ -387,6 +414,143 @@ frame@b128000 { >> status = "disabled"; >> }; >> }; >> + >> + pcie0: pci@80000000 { > > pcie@ > ok >> + compatible = "qcom,pcie-ipq5018"; >> + reg = <0x80000000 0xf1d>, >> + <0x80000f20 0xa8>, >> + <0x80001000 0x1000>, >> + <0x00078000 0x3000>, >> + <0x80100000 0x1000>; > > Are you sure that the config space is only 4K? > ok, let me double check. >> + reg-names = "dbi", "elbi", "atu", "parf", "config"; >> + device_type = "pci"; >> + linux,pci-domain = <0>; >> + bus-range = <0x00 0xff>; >> + num-lanes = <1>; >> + max-link-speed = <2>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + phys = <&pcie_x1phy>; >> + phy-names ="pciephy"; >> + >> + ranges = <0x01000000 0 0x80200000 0x80200000 0 0x00100000 > > Please check the value of this field in other SoCs. ok, if its about the child address encoding for IO region, will fix. > >> + 0x02000000 0 0x80300000 0x80300000 0 0x10000000>; >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0x7>; >> + interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>; >> + >> + interrupts = ; >> + interrupt-names = "global_irq"; > > I'm pretty sure that this SoC has SPI based MSI interrupts. So they should be > described even though ITS is supported. ok > >> + >> + clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, >> + <&gcc GCC_PCIE1_AXI_M_CLK>, >> + <&gcc GCC_PCIE1_AXI_S_CLK>, >> + <&gcc GCC_PCIE1_AHB_CLK>, >> + <&gcc GCC_PCIE1_AUX_CLK>, >> + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; >> + >> + clock-names = "iface", >> + "axi_m", >> + "axi_s", >> + "ahb", >> + "aux", >> + "axi_bridge"; >> + >> + resets = <&gcc GCC_PCIE1_PIPE_ARES>, >> + <&gcc GCC_PCIE1_SLEEP_ARES>, >> + <&gcc GCC_PCIE1_CORE_STICKY_ARES>, >> + <&gcc GCC_PCIE1_AXI_MASTER_ARES>, >> + <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, >> + <&gcc GCC_PCIE1_AHB_ARES>, >> + <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, >> + <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; >> + >> + reset-names = "pipe", >> + "sleep", >> + "sticky", >> + "axi_m", >> + "axi_s", >> + "ahb", >> + "axi_m_sticky", >> + "axi_s_sticky"; >> + >> + msi-map = <0x0 &v2m0 0x0 0xff8>; >> + status = "disabled"; > > Please add the rootport node also as like other SoCs. > ok > Above comments applies to below PCIe node. > ok Regards, Sricharan -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy