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Fri, 13 Jun 2025 07:48:27 -0700 (PDT) Received: from geday ([2804:7f2:800b:838f::dead:c001]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2fe164406esm1803644a12.27.2025.06.13.07.48.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jun 2025 07:48:26 -0700 (PDT) Date: Fri, 13 Jun 2025 11:48:21 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 0/4] PCI: rockchip: Improve quality of driver Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250613_074828_164958_D44D453D X-CRM114-Status: UNSURE ( 7.35 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org During a 30-day debugging-run fighting quirky PCIe devices on RK3399 some quality improvements began to take form and this is my attempt at upstreaming it. It will ensure maximum chance of retraining to Gen2 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0] without risk of locking up kernel like with present broken async strobe TEST_WRITE. --- V3 -> V4: fix TLS setting-up in Link Control and Status Register 2 and adjust commit titles V2 -> V3: correctly clean-up with standard PCIe defines as per Bjorn's suggestion V1 -> V2: use standard PCIe defines as suggested by Bjorn Geraldo Nascimento (4): PCI: rockchip: Drop unused custom registers and bitfields PCI: rockchip: Set Target Link Speed before retraining phy: rockchip-pcie: Enable all four lanes phy: rockchip-pcie: Adjust read mask and write drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ drivers/pci/controller/pcie-rockchip.h | 11 +---------- drivers/phy/rockchip/phy-rockchip-pcie.c | 16 +++++++++------- 3 files changed, 14 insertions(+), 17 deletions(-) -- 2.49.0 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy