From: Josua Mayer <josua@solid-run.com>
To: Vladimir Oltean <vladimir.oltean@nxp.com>
Cc: "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
Ioana Ciornei <ioana.ciornei@nxp.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 phy 15/16] phy: lynx-28g: truly power the lanes up or down
Date: Wed, 24 Sep 2025 15:57:56 +0000 [thread overview]
Message-ID: <d0c8bbf8-a0c5-469f-a148-de2235948c0f@solid-run.com> (raw)
In-Reply-To: <20250924130654.nnliddqiug5hkbsh@skbuf>
Am 24.09.25 um 15:06 schrieb Vladimir Oltean:
> On Wed, Sep 24, 2025 at 10:09:26AM +0000, Josua Mayer wrote:
>> Unbounded loop, perhaps use timeout.
>>
>> This can fail on unbalanced calls as you discovered,
>> but also e.g. when a pll is unstable.
>>
>> See below for when this came up previously:
>>
>> https://lore.kernel.org/all/20240218-lynx28g-infinite-loop-v1-1-59cc5cef8367@solid-run.com/
> Ok, I can make this a 17-patch set, no problem.
>
> What happened to your patch? Did it get lost?
I suspect I got distracted and never sent a v2.
> Do you mind if I write a
> new one myself, with a single read_poll_timeout() call for both
> LNaTRSTCTL and LNaRRSTCTL, to keep the functionality same as before?
Sure, feel free.
Since tx and rx are in different registers you will still need to poll each one?
--
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next prev parent reply other threads:[~2025-09-24 15:58 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-23 19:44 [PATCH v2 phy 00/16] Lynx 28G improvements part 1 Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 01/16] phy: lynx-28g: remove LYNX_28G_ prefix from register names Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 02/16] phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg" with "val" and "mask" Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 03/16] phy: lynx-28g: use FIELD_GET() and FIELD_PREP() Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 04/16] phy: lynx-28g: convert iowrite32() calls with magic values to macros Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 05/16] phy: lynx-28g: restructure protocol configuration register accesses Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 06/16] phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 07/16] phy: lynx-28g: refactor lane->interface to lane->mode Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 08/16] phy: lynx-28g: distinguish between 10GBASE-R and USXGMII Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 09/16] phy: lynx-28g: configure more equalization params for 1GbE and 10GbE Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 10/16] phy: lynx-28g: use "dev" argument more in lynx_28g_probe() Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 11/16] phy: lynx-28g: improve lynx_28g_probe() sequence Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 12/16] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation Vladimir Oltean
2025-09-23 20:37 ` Rob Herring (Arm)
2025-09-23 20:57 ` Vladimir Oltean
2025-09-24 13:54 ` Rob Herring
2025-09-24 15:45 ` Vladimir Oltean
2025-09-24 15:56 ` Josua Mayer
2025-09-25 8:03 ` Vladimir Oltean
2025-09-25 13:05 ` Rob Herring
2025-09-23 19:44 ` [PATCH v2 phy 13/16] phy: lynx-28g: probe on per-SoC and per-instance compatible strings Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 14/16] phy: lynx-28g: add support for 25GBASER Vladimir Oltean
2025-09-23 19:44 ` [PATCH v2 phy 15/16] phy: lynx-28g: truly power the lanes up or down Vladimir Oltean
2025-09-24 10:09 ` Josua Mayer
2025-09-24 13:06 ` Vladimir Oltean
2025-09-24 15:57 ` Josua Mayer [this message]
2025-09-23 19:44 ` [PATCH v2 phy 16/16] phy: lynx-28g: implement phy_exit() operation Vladimir Oltean
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