Re: [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY for X1E80100

[Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>]

Hi George,

We've been working on C-PHY enablement for the same qcom-mipi-csi2
driver (SA8775P/QCS8300/SC7280) and have already posted earlier versions
of our series trailing David's patches, ran into the same
file-organisation question this patch raises.
Link:
https://lore.kernel.org/all/20260717231331.1229693-1-anusha.nandi@oss.qualcomm.com/

One structural difference worth syncing on: this patch adds the X1E80100
C-PHY register sequence and hw-ops directly into
phy-qcom-mipi-csi2-3ph-dphy.c, growing the existing D-PHY file. In our
series we split C-PHY hw-ops into a dedicated
phy-qcom-mipi-csi2-3ph-cphy.c (mirroring the existing -3ph-dphy.c
split), so:

1. The D-PHY file stays D-PHY-only and doesn't grow with every new C-PHY
SoC added later.
2. Adding a new SoC's C-PHY register table only touches the C-PHY file,
with no risk of an unrelated D-PHY regression in the same patch/file.
3. The two PHY-type code paths (register tables, lane/polarity handling,
settle-count calc) stay independently reviewable instead of interleaved
in one growing file.

Our series is here:
https://lore.kernel.org/all/20261017035221.3816464-1-anusha.nandi@oss.qualcomm.com/
https://lore.kernel.org/all/20261017040529.3832120-1-anusha.nandi@oss.qualcomm.com/
https://lore.kernel.org/all/20261017041733.3946816-1-anusha.nandi@oss.qualcomm.com/

Happy to discuss further and compare both approaches.

Best Regards,
Anusha Arun Nandi

On 10/16/2026 7:56 AM, George Neacsu via B4 Relay wrote:
> Hi Bryan, Vinod, David,
> 
> The Snapdragon Surface Pro 11's front camera, an IMX681, is on CSIPHY2
> over one MIPI C-PHY trio. linux-next has the CSI2 PHY driver and the CAMSS
> PHY API path, and C-PHY is the piece still missing for this camera. This
> series adds the PHY side:
> 
> 1. PHY_MODE_MIPI_CPHY and C-PHY configuration options in the generic PHY
>    framework, because CAMSS had no way to ask the PHY for C-PHY;
> 2. C-PHY configuration helpers, the analogue of
>    phy_mipi_dphy_get_default_config_for_hsclk();
> 3. a rename of the D-PHY init sequence in qcom-mipi-csi2;
> 4. lane mask and lane polarity helpers in qcom-mipi-csi2, with no
>    functional change;
> 5. fsleep() for the init sequence delays, the same udelay() for the
>    current D-PHY sequence;
> 6. C-PHY in qcom-mipi-csi2, with the X1E80100 sequence taken from
>    Qualcomm's GPL-2.0 downstream header.
> 
> The series is on next-20261015 and applies there on its own. The two
> CAMSS patches that use it build on David's "media: camss: Add support
> for C-PHY configuration on Qualcomm platforms" v9, which is not in
> linux-next yet, so I will send them on top of David's series:
> https://lore.kernel.org/all/20260729-qcom-cphy-v9-0-1f8d9fdab037@ixit.cz/
> 
> Tested on the Surface Pro 11 (X1E80100), booting next-20261015 with this
> series, David's v9 and those two CAMSS patches on top, with CSI2 PHY
> nodes as in Bryan's x1e80100 camera DT v7, CAMSS in PHY API mode, and raw
> capture over RDI:
> - front IMX681 (Sergey's and Andre's v8 driver plus its C-PHY RFC) on
>   CSIPHY2, one C-PHY trio at 2.4 Gsym/s: 3844x2640 at 30 fps, and the
>   sensor's colour bars are byte-identical to the pattern captured with an
>   out-of-tree driver. The settle count is computed, 28 at a 400 MHz
>   timer;
> - rear OV13858 on CSIPHY1, four D-PHY lanes: 29.9 fps.
> On the earlier test setup, linux-next's CAMSS and CSI2 PHY as modules on
> 7.1.5, forcing any settle count from 6 to 48 gave the same frames.
> 
> Open question, from Nihal: the X1E table is Qualcomm's 2.5 Gsps one, and
> downstream picks C-PHY settings by symbol rate. I would keep a single
> table here and add selection by rate when a second rate is needed,
> unless you would rather have the structure now.
> 
> Thanks,
> George
> 
> ---
> Changes in v3:
> - Drop the RFC prefix (Bryan)
> - Test on a linux-next kernel instead of linux-next's modules on 7.1.5
>   (Bryan)
> - phy: u64 and u8 in struct phy_configure_opts_mipi_cphy and the
>   helpers (sashiko); pick up Reviewed-by tags from Loic and Bryan
> - qcom-mipi-csi2: split the lane mask and polarity helpers and the
>   fsleep() change out of the C-PHY patch, each with no functional change
>   for D-PHY
> - qcom-mipi-csi2: write the C-PHY per-trio register addresses with
>   CSIPHY_LN_CTRLn(); the object code is unchanged (David)
> - Link to v2: https://lore.kernel.org/r/20261016-x1e-cphy-rfc-v2-0-377654253193@gmail.com
> 
> Changes in v2:
> - Rebase on next-20261015, PHY patches only; the CAMSS patches follow
>   David's series (Bryan)
> - phy: rename lanes to trios (Loic), make symbol_rate unsigned long long
>   so 32-bit can hold rates above 4.29 Gsym/s, and keep Bryan's R-b for
>   that patch
> - phy: new patch with the C-PHY helpers (Bryan, Loic)
> - qcom-mipi-csi2: new patch renaming init_seq/lane_array_size to
>   dphy_init_seq/dphy_lane_array_size (Bryan)
> - qcom-mipi-csi2: rename the C-PHY table to lane_regs_v2_1_2_cphy and
>   shorten its comment (Konrad)
> - qcom-mipi-csi2: no separate bus_type; the endpoint sets phy_mode and
>   set_mode() checks against it (Nihal)
> - qcom-mipi-csi2: if/else instead of the ternaries, one declaration per
>   line, and lanes_enable() split into lane mask and polarity helpers
>   instead of the goto (Bryan, Nihal)
> - qcom-mipi-csi2: configure() uses the helpers and keeps the link
>   frequency, so clocks scale as for D-PHY
> - qcom-mipi-csi2: compute the C-PHY settle count instead of the fixed
>   table value; blank lines between the per-trio blocks; fsleep() for the
>   sequence delays (Nihal)
> - qcom-mipi-csi2: drop the video-interfaces.h include, no longer needed
> - Link to v1: https://lore.kernel.org/r/20261015-x1e-cphy-rfc-v1-0-1f3fa9af940a@gmail.com
> 
> ---
> George Neacsu (6):
>       phy: Add MIPI C-PHY mode and configuration options
>       phy: Add MIPI C-PHY configuration helpers
>       phy: qcom-mipi-csi2: Rename the D-PHY init sequence
>       phy: qcom-mipi-csi2: Add lane mask and lane polarity helpers
>       phy: qcom-mipi-csi2: Use fsleep() for init sequence delays
>       phy: qcom-mipi-csi2: Add C-PHY support for X1E80100
> 
>  drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 228 ++++++++++++++++++---
>  drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c     |  53 ++++-
>  drivers/phy/qualcomm/phy-qcom-mipi-csi2.h          |   6 +-
>  include/linux/phy/phy-mipi-cphy.h                  |  89 ++++++++
>  include/linux/phy/phy.h                            |   5 +
>  5 files changed, 348 insertions(+), 33 deletions(-)
> ---
> base-commit: b810335a0699d1810683796b0e3ffe8827ddfe6c
> change-id: 20261015-x1e-cphy-rfc-201860c8097f
> 
> Best regards,


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