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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 9/21/26 8:30 AM, Qiang Yu wrote: > On Mon, Sep 21, 2026 at 11:07:08AM +0530, Krishna Chaitanya Chundru wrote: >> This series adds PCIe support for the Qualcomm Nord (SA8797P) platform. >> >> Nord has a single Gen5-capable QMP PCIe PHY block split into four >> independently-clocked and independently-resettable ports (A/B/C/D). >> Firmware selects the active lane topology at boot via a TCSR >> configuration register, and the same PHY block can appear as a single >> x16 port, x8+x8, x8+x4+x4, or x8+x4+x2+x2 depending on that mode. This >> is similar in spirit to the Glymur multi-PHY support already posted, >> except Nord's PHY registers are programmed by Linux rather than by >> firmware, so this series adds the PLL, TXRXZ, PCS and PCS-lane init >> tables along with the power-up/power-down/soft-reset sequencing needed >> to bring each port up. >> >> The series also documents and wires up the qcom,nord-pcie compatible >> (reusing the existing SA8775P PCIe controller binding), and adds a >> CORE_CLK_CGC_DIS/AUX_PWR_DET workaround required to avoid a timing >> convergence issue in the PCIe power domain. >> >> Signed-off-by: Krishna Chaitanya Chundru > > Tested on Glymur CRD and Glymur QCB, devices can be enumerated. A test of "this didn't break my completely different board" is welcome, but looks a little confusing without you saying that was the intent specifically - unless maybe it wasn't? Konrad -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy