* [PATCH v8 1/7] dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
@ 2025-10-23 13:58 ` Claudiu
2025-10-23 13:58 ` [PATCH v8 2/7] phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe() Claudiu
` (8 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Claudiu @ 2025-10-23 13:58 UTC (permalink / raw)
To: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: claudiu.beznea, linux-phy, devicetree, linux-kernel,
linux-renesas-soc, Claudiu Beznea, Conor Dooley
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The reset lines are mandatory for the Renesas RZ/G3S platform and must be
explicitly defined in device tree.
Fixes: f3c849855114 ("dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings")
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v8:
- none
Changes in v7:
- dropped Tb tag as it was reported that it is not valid on bindings
Changes in v6:
- collected tags
Changes in v5:
- none
Changes in v4:
- none
Changes in v3:
- collected tags
- rebased on top of latest version of renesas,usb2-phy.yaml;
Conor, Geert: I kept your tags; please let me know if you consider it
otherwise
Changes in v2:
- none; this patch is new
Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index 179cb4bfc424..2bbec8702a1e 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -118,6 +118,7 @@ allOf:
contains:
enum:
- renesas,usb2-phy-r9a09g057
+ - renesas,usb2-phy-r9a08g045
- renesas,rzg2l-usb2-phy
then:
properties:
--
2.43.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 2/7] phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe()
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
2025-10-23 13:58 ` [PATCH v8 1/7] dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S Claudiu
@ 2025-10-23 13:58 ` Claudiu
2025-10-23 13:58 ` [PATCH v8 3/7] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support Claudiu
` (7 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Claudiu @ 2025-10-23 13:58 UTC (permalink / raw)
To: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: claudiu.beznea, linux-phy, devicetree, linux-kernel,
linux-renesas-soc, Christophe JAILLET, Wolfram Sang,
Claudiu Beznea
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
If an error occurs after the reset_control_deassert(),
reset_control_assert() must be called, as already done in the remove
function.
Use devm_add_action_or_reset() to add the missing call and simplify the
.remove() function accordingly.
While at it, drop struct rcar_gen3_chan::rstc as it is not used aymore.
Fixes: 4eae16375357 ("phy: renesas: rcar-gen3-usb2: Add support to initialize the bus")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[claudiu.beznea: removed "struct reset_control *rstc = data;" from
rcar_gen3_reset_assert(), dropped struct rcar_gen3_chan::rstc]
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v8:
- none
Changes in v7:
- none
Changes in v6:
- dropped struct rcar_gen3_chan::rstc; updated the patch description
to reflect it
- collected tags
Changes in v5:
- none
Changes in v4:
- none
Changes in v3:
- collected tags
Changes in v2:
- none; this patch is new; re-spinned the Christophe's work at
https://lore.kernel.org/all/TYCPR01MB113329930BA5E2149C9BE2A1986672@TYCPR01MB11332.jpnprd01.prod.outlook.com/
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index 3f6b480e1092..a38ead7c8055 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -134,7 +134,6 @@ struct rcar_gen3_chan {
struct extcon_dev *extcon;
struct rcar_gen3_phy rphys[NUM_OF_PHYS];
struct regulator *vbus;
- struct reset_control *rstc;
struct work_struct work;
spinlock_t lock; /* protects access to hardware and driver data structure. */
enum usb_dr_mode dr_mode;
@@ -771,21 +770,31 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np)
return candidate;
}
+static void rcar_gen3_reset_assert(void *data)
+{
+ reset_control_assert(data);
+}
+
static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel)
{
struct device *dev = channel->dev;
+ struct reset_control *rstc;
int ret;
u32 val;
- channel->rstc = devm_reset_control_array_get_shared(dev);
- if (IS_ERR(channel->rstc))
- return PTR_ERR(channel->rstc);
+ rstc = devm_reset_control_array_get_shared(dev);
+ if (IS_ERR(rstc))
+ return PTR_ERR(rstc);
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
- ret = reset_control_deassert(channel->rstc);
+ ret = reset_control_deassert(rstc);
+ if (ret)
+ goto rpm_put;
+
+ ret = devm_add_action_or_reset(dev, rcar_gen3_reset_assert, rstc);
if (ret)
goto rpm_put;
@@ -924,7 +933,6 @@ static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev)
if (channel->is_otg_channel)
device_remove_file(&pdev->dev, &dev_attr_role);
- reset_control_assert(channel->rstc);
pm_runtime_disable(&pdev->dev);
};
--
2.43.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 3/7] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
2025-10-23 13:58 ` [PATCH v8 1/7] dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S Claudiu
2025-10-23 13:58 ` [PATCH v8 2/7] phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe() Claudiu
@ 2025-10-23 13:58 ` Claudiu
2025-10-23 13:58 ` [PATCH v8 4/7] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY Claudiu
` (6 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Claudiu @ 2025-10-23 13:58 UTC (permalink / raw)
To: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: claudiu.beznea, linux-phy, devicetree, linux-kernel,
linux-renesas-soc, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The Renesas USB PHY hardware block needs to have the PWRRDY bit in the
system controller set before applying any other settings. The PWRRDY bit
must be controlled during power-on, power-off, and system suspend/resume
sequences as follows:
- during power-on/resume, it must be set to zero before enabling clocks and
modules
- during power-off/suspend, it must be set to one after disabling clocks
and modules
Add the renesas,sysc-pwrrdy device tree property, which allows the
reset-rzg2l-usbphy-ctrl driver to parse, map, and control the system
controller PWRRDY bit at the appropriate time. Along with it add a new
compatible for the RZ/G3S SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v8:
- none
Changes in v7:
- dropped Tb tag as it was reported that it is not valid on bindings
Changes in v6:
- collected tags
Changes in v5:
- fixed description formatting
- collected tags
Changes in v4:
- dropped blank line from compatible section
- s/renesas,sysc-signals/renesas,sysc-pwrrdy/g
- dropped description from renesas,sysc-pwrrdy
- updated description of renesas,sysc-pwrrdy items
- updated patch description
Changes in v3:
- none; this patch is new
.../reset/renesas,rzg2l-usbphy-ctrl.yaml | 41 ++++++++++++++++---
1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
index b0b20af15313..c83469a1b379 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
+++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
@@ -15,12 +15,14 @@ description:
properties:
compatible:
- items:
- - enum:
- - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
- - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
- - renesas,r9a07g054-usbphy-ctrl # RZ/V2L
- - const: renesas,rzg2l-usbphy-ctrl
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
+ - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
+ - renesas,r9a07g054-usbphy-ctrl # RZ/V2L
+ - const: renesas,rzg2l-usbphy-ctrl
+ - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S
reg:
maxItems: 1
@@ -48,6 +50,20 @@ properties:
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
+ renesas,sysc-pwrrdy:
+ description:
+ The system controller PWRRDY indicates to the USB PHY if the power supply
+ is ready. PWRRDY needs to be set during power-on before applying any
+ other settings. It also needs to be set before powering off the USB.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description:
+ System controller phandle required by USB PHY CTRL driver to set
+ PWRRDY
+ - description: Register offset associated with PWRRDY
+ - description: Register bitmask associated with PWRRDY
+
required:
- compatible
- reg
@@ -57,6 +73,19 @@ required:
- '#reset-cells'
- regulator-vbus
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a08g045-usbphy-ctrl
+ then:
+ required:
+ - renesas,sysc-pwrrdy
+ else:
+ properties:
+ renesas,sysc-pwrrdy: false
+
additionalProperties: false
examples:
--
2.43.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 4/7] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
` (2 preceding siblings ...)
2025-10-23 13:58 ` [PATCH v8 3/7] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support Claudiu
@ 2025-10-23 13:58 ` Claudiu
2025-10-24 9:30 ` Philipp Zabel
2025-10-23 13:58 ` [PATCH v8 5/7] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC Claudiu
` (5 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Claudiu @ 2025-10-23 13:58 UTC (permalink / raw)
To: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: claudiu.beznea, linux-phy, devicetree, linux-kernel,
linux-renesas-soc, Claudiu Beznea, Wolfram Sang
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called
PWRRDY. This signal is managed by the system controller and must be
de-asserted after powering on the area where USB PHY resides and asserted
before powering it off.
On power-on/resume the USB PWRRDY signal need to be de-asserted before
enabling clock and switching the module to normal state (through MSTOP
support). The power-on/resume configuration sequence must be:
1/ PWRRDY=0
2/ CLK_ON=1
3/ MSTOP=0
On power-off/suspend the configuration sequence should be:
1/ MSTOP=1
2/ CLK_ON=0
3/ PWRRDY=1
The CLK_ON and MSTOP functionalities are controlled by clock drivers.
The suspend/resume support will be handled by different patches.
After long discussions with the internal HW team, it has been confirmed
that the HW connection b/w USB PHY block, the USB channels, the system
controller, clock, MSTOP, PWRRDY signal is as follows:
┌──────────────────────────────┐
│ │◄── CPG_CLKON_USB.CLK0_ON
│ USB CH0 │
┌──────────────────────────┐ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK2_ON
│ ┌────────┐ ││host controller registers │ │
│ │ │ ││function controller registers│
│ │ PHY0 │◄──┤└───────────────────────────┘ │
│ USB PHY │ │ └────────────▲─────────────────┘
│ └────────┘ │
│ │ CPG_BUS_PERI_COM_MSTOP.MSTOP{6, 5}_ON
│┌──────────────┐ ┌────────┐
││USHPHY control│ │ │
││ registers │ │ PHY1 │ ┌──────────────────────────────┐
│└──────────────┘ │ │◄──┤ USB CH1 │
│ └────────┘ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK1_ON
└─▲───────▲─────────▲──────┘ ││ host controller registers │ │
│ │ │ │└───────────────────────────┘ │
│ │ │ └────────────▲─────────────────┘
│ │ │ │
│ │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP7_ON
│PWRRDY │ │
│ │ CPG_CLK_ON_USB.CLK3_ON
│ │
│ CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON
│
┌────┐
│SYSC│
└────┘
where:
- CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X
of different USB blocks, X in {0, 1, 2, 3}
- CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the
MSTOP of different USB blocks, X in {4, 5, 6, 7}
- USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used
by the USB CH0, USB CH1
- SYSC is the system controller block controlling the PWRRDY signal
- USB CHx are individual USB block with host and function capabilities
(USB CH0 have both host and function capabilities, USB CH1 has only
host capabilities)
The USBPHY control registers are controlled though the
reset-rzg2l-usbphy-ctrl driver. The USB PHY ports are controlled by
phy_rcar_gen3_usb2 (drivers/phy/renesas/phy-rcar-gen3-usb2.c file). The
USB PHY ports request resets from the reset-rzg2l-usbphy-ctrl driver.
The connection b/w the system controller and the USB PHY CTRL driver is
implemented through the renesas,sysc-pwrrdy device tree property
proposed in this patch. This property specifies the register offset and the
bitmask required to control the PWRRDY signal.
Since the USB PHY CTRL driver needs to be probed before any other
USB-specific driver on RZ/G3S, control of PWRRDY is passed exclusively
to it. This guarantees the correct configuration sequence between clocks,
MSTOP bits, and the PWRRDY bit on probe/resume and remove/suspend. At the
same time, changes are kept minimal by avoiding modifications to the USB
PHY driver to also handle the PWRRDY itself.
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v8:
- updated the patch description to emphasize that PWRRDY need to be
controlled on suspend/resume path, as well (when support will be
proposed)
- dropped struct rzg2l_usbphy_ctrl_pwrrdy and used regmap_field
instead
- simplified the logic in rzg2l_usbphy_ctrl_set_pwrrdy() by relying
on the fact that PWRRDY mask provided though device tree will
always be 1 bit long
- in rzg2l_usbphy_ctrl_pwrrdy_init() cast data to uintptr_t before
comparing it with a constant
Changes in v7:
- used proper regmap update value on rzg2l_usbphy_ctrl_set_pwrrdy()
Changes in v6:
- used syscon_regmap_lookup_by_phandle_args() to simplify the code
- collected tags
Changes in v5:
- none
Changes in v4:
- updated patch description
- updated rzg2l_usbphy_ctrl_pwrrdy_init() to map directly the
"renesas,sysc-pwrrdy" as the SYSC signal abstraction was dropped
in this version, along with rz_sysc_get_signal_map()
- dropped priv member of rzg2l_usbphy_ctrl_pwrrdy_init() as it is
not needed in this version
- shift left !power_on with pwrrdy->mask as this is how the
regmap_update_bits() needs the last member to be
- selected MFD_SYSCON
Changes in v3:
- none; this patch is new
drivers/reset/Kconfig | 1 +
drivers/reset/reset-rzg2l-usbphy-ctrl.c | 56 +++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 78b7078478d4..329730cbcfb9 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -237,6 +237,7 @@ config RESET_RASPBERRYPI
config RESET_RZG2L_USBPHY_CTRL
tristate "Renesas RZ/G2L USBPHY control driver"
depends on ARCH_RZG2L || COMPILE_TEST
+ select MFD_SYSCON
help
Support for USBPHY Control found on RZ/G2L family. It mainly
controls reset and power down of the USB/PHY.
diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
index 8a7f167e405e..57350764be25 100644
--- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -13,6 +13,7 @@
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
#define RESET 0x000
#define VBENCTL 0x03c
@@ -91,6 +92,8 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
return !!(readl(priv->base + RESET) & port_mask);
}
+#define RZG2L_USBPHY_CTRL_PWRRDY 1
+
static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
{ .compatible = "renesas,rzg2l-usbphy-ctrl" },
{ /* Sentinel */ }
@@ -110,6 +113,55 @@ static const struct regmap_config rzg2l_usb_regconf = {
.max_register = 1,
};
+static void rzg2l_usbphy_ctrl_set_pwrrdy(struct regmap_field *pwrrdy,
+ bool power_on)
+{
+ u32 val = power_on ? 0 : 1;
+
+ /* The initialization path guarantees that the mask is 1 bit long. */
+ regmap_field_update_bits(pwrrdy, 1, val);
+}
+
+static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data)
+{
+ rzg2l_usbphy_ctrl_set_pwrrdy(data, false);
+}
+
+static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev)
+{
+ struct regmap_field *pwrrdy;
+ struct reg_field field;
+ struct regmap *regmap;
+ const int *data;
+ u32 args[2];
+
+ data = device_get_match_data(dev);
+ if ((uintptr_t)data != RZG2L_USBPHY_CTRL_PWRRDY)
+ return 0;
+
+ regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
+ "renesas,sysc-pwrrdy",
+ ARRAY_SIZE(args), args);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /* Don't allow more than one bit in mask. */
+ if (hweight32(args[1]) != 1)
+ return -EINVAL;
+
+ field.reg = args[0];
+ field.lsb = __ffs(args[1]);
+ field.msb = __fls(args[1]);
+
+ pwrrdy = devm_regmap_field_alloc(dev, regmap, field);
+ if (!pwrrdy)
+ return -ENOMEM;
+
+ rzg2l_usbphy_ctrl_set_pwrrdy(pwrrdy, true);
+
+ return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, pwrrdy);
+}
+
static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -132,6 +184,10 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
+ error = rzg2l_usbphy_ctrl_pwrrdy_init(dev);
+ if (error)
+ return error;
+
priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(priv->rstc))
return dev_err_probe(dev, PTR_ERR(priv->rstc),
--
2.43.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v8 4/7] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
2025-10-23 13:58 ` [PATCH v8 4/7] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY Claudiu
@ 2025-10-24 9:30 ` Philipp Zabel
0 siblings, 0 replies; 17+ messages in thread
From: Philipp Zabel @ 2025-10-24 9:30 UTC (permalink / raw)
To: Claudiu, vkoul, kishon, robh, krzk+dt, conor+dt, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: linux-phy, devicetree, linux-kernel, linux-renesas-soc,
Claudiu Beznea, Wolfram Sang
On Do, 2025-10-23 at 16:58 +0300, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called
> PWRRDY. This signal is managed by the system controller and must be
> de-asserted after powering on the area where USB PHY resides and asserted
> before powering it off.
>
> On power-on/resume the USB PWRRDY signal need to be de-asserted before
> enabling clock and switching the module to normal state (through MSTOP
> support). The power-on/resume configuration sequence must be:
>
> 1/ PWRRDY=0
> 2/ CLK_ON=1
> 3/ MSTOP=0
>
> On power-off/suspend the configuration sequence should be:
>
> 1/ MSTOP=1
> 2/ CLK_ON=0
> 3/ PWRRDY=1
>
> The CLK_ON and MSTOP functionalities are controlled by clock drivers.
> The suspend/resume support will be handled by different patches.
>
> After long discussions with the internal HW team, it has been confirmed
> that the HW connection b/w USB PHY block, the USB channels, the system
> controller, clock, MSTOP, PWRRDY signal is as follows:
>
> ┌──────────────────────────────┐
> │ │◄── CPG_CLKON_USB.CLK0_ON
> │ USB CH0 │
> ┌──────────────────────────┐ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK2_ON
> │ ┌────────┐ ││host controller registers │ │
> │ │ │ ││function controller registers│
> │ │ PHY0 │◄──┤└───────────────────────────┘ │
> │ USB PHY │ │ └────────────▲─────────────────┘
> │ └────────┘ │
> │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP{6, 5}_ON
> │┌──────────────┐ ┌────────┐
> ││USHPHY control│ │ │
> ││ registers │ │ PHY1 │ ┌──────────────────────────────┐
> │└──────────────┘ │ │◄──┤ USB CH1 │
> │ └────────┘ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK1_ON
> └─▲───────▲─────────▲──────┘ ││ host controller registers │ │
> │ │ │ │└───────────────────────────┘ │
> │ │ │ └────────────▲─────────────────┘
> │ │ │ │
> │ │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP7_ON
> │PWRRDY │ │
> │ │ CPG_CLK_ON_USB.CLK3_ON
> │ │
> │ CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON
> │
> ┌────┐
> │SYSC│
> └────┘
>
> where:
> - CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X
> of different USB blocks, X in {0, 1, 2, 3}
> - CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the
> MSTOP of different USB blocks, X in {4, 5, 6, 7}
> - USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used
> by the USB CH0, USB CH1
> - SYSC is the system controller block controlling the PWRRDY signal
> - USB CHx are individual USB block with host and function capabilities
> (USB CH0 have both host and function capabilities, USB CH1 has only
> host capabilities)
>
> The USBPHY control registers are controlled though the
> reset-rzg2l-usbphy-ctrl driver. The USB PHY ports are controlled by
> phy_rcar_gen3_usb2 (drivers/phy/renesas/phy-rcar-gen3-usb2.c file). The
> USB PHY ports request resets from the reset-rzg2l-usbphy-ctrl driver.
>
> The connection b/w the system controller and the USB PHY CTRL driver is
> implemented through the renesas,sysc-pwrrdy device tree property
> proposed in this patch. This property specifies the register offset and the
> bitmask required to control the PWRRDY signal.
>
> Since the USB PHY CTRL driver needs to be probed before any other
> USB-specific driver on RZ/G3S, control of PWRRDY is passed exclusively
> to it. This guarantees the correct configuration sequence between clocks,
> MSTOP bits, and the PWRRDY bit on probe/resume and remove/suspend. At the
> same time, changes are kept minimal by avoiding modifications to the USB
> PHY driver to also handle the PWRRDY itself.
>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
regards
Philipp
--
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v8 5/7] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
` (3 preceding siblings ...)
2025-10-23 13:58 ` [PATCH v8 4/7] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY Claudiu
@ 2025-10-23 13:58 ` Claudiu
2025-10-24 9:30 ` Philipp Zabel
2025-10-23 13:58 ` [PATCH v8 6/7] arm64: dts: renesas: r9a08g045: Add USB support Claudiu
` (4 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Claudiu @ 2025-10-23 13:58 UTC (permalink / raw)
To: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: claudiu.beznea, linux-phy, devicetree, linux-kernel,
linux-renesas-soc, Claudiu Beznea, Wolfram Sang
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The Renesas RZ/G3S SoC USB PHY HW block receives as input the USB PWRRDY
signal from the system controller. Add support for the Renesas RZ/G3S SoC.
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v8:
- none
Changes in v7:
- none
Changes in v6:
- collected tags
Changes in v5:
- none
Changes in v4:
- none
Changes in v3:
- none; this patch is new
drivers/reset/reset-rzg2l-usbphy-ctrl.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
index 57350764be25..1c0424639e66 100644
--- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -96,6 +96,10 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
{ .compatible = "renesas,rzg2l-usbphy-ctrl" },
+ {
+ .compatible = "renesas,r9a08g045-usbphy-ctrl",
+ .data = (void *)RZG2L_USBPHY_CTRL_PWRRDY
+ },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table);
--
2.43.0
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v8 5/7] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
2025-10-23 13:58 ` [PATCH v8 5/7] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC Claudiu
@ 2025-10-24 9:30 ` Philipp Zabel
0 siblings, 0 replies; 17+ messages in thread
From: Philipp Zabel @ 2025-10-24 9:30 UTC (permalink / raw)
To: Claudiu, vkoul, kishon, robh, krzk+dt, conor+dt, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: linux-phy, devicetree, linux-kernel, linux-renesas-soc,
Claudiu Beznea, Wolfram Sang
On Do, 2025-10-23 at 16:58 +0300, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The Renesas RZ/G3S SoC USB PHY HW block receives as input the USB PWRRDY
> signal from the system controller. Add support for the Renesas RZ/G3S SoC.
>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
regards
Philipp
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v8 6/7] arm64: dts: renesas: r9a08g045: Add USB support
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
` (4 preceding siblings ...)
2025-10-23 13:58 ` [PATCH v8 5/7] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC Claudiu
@ 2025-10-23 13:58 ` Claudiu
2025-11-13 15:04 ` Geert Uytterhoeven
2025-10-23 13:58 ` [PATCH v8 7/7] arm64: dts: renesas: rzg3s-smarc: Enable " Claudiu
` (3 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Claudiu @ 2025-10-23 13:58 UTC (permalink / raw)
To: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: claudiu.beznea, linux-phy, devicetree, linux-kernel,
linux-renesas-soc, Claudiu Beznea, Wolfram Sang
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset,
host and device support.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v8:
- none
Changes in v7:
- collected tags
Changes in v6:
- collected tags
Changes in v5:
- none
Changes in v4:
- dropped renesas,sysc-signals from usb2_phy0, usb2_phy1 nodes
- s/renesas,sysc-signals/renesas,sysc-pwrrdy/g
Changes in v3:
- changed the nodes order to keep similar nodes toghether
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 118 +++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index dd9c9c33d9d6..876de634908e 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -727,6 +727,124 @@ eth1: ethernet@11c40000 {
status = "disabled";
};
+ phyrst: usbphy-ctrl@11e00000 {
+ compatible = "renesas,r9a08g045-usbphy-ctrl";
+ reg = <0 0x11e00000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>;
+ resets = <&cpg R9A08G045_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ renesas,sysc-pwrrdy = <&sysc 0xd70 0x1>;
+ status = "disabled";
+
+ usb0_vbus_otg: regulator-vbus {
+ regulator-name = "vbus";
+ };
+ };
+
+ ohci0: usb@11e10000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11e10000 0 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A08G045_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@11e30000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11e30000 0 0x100>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A08G045_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@11e10100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11e10100 0 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A08G045_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@11e30100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11e30100 0 0x100>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A08G045_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@11e10200 {
+ compatible = "renesas,usb2-phy-r9a08g045";
+ reg = <0 0x11e10200 0 0x700>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A08G045_USB_U2H0_HRESETN>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@11e30200 {
+ compatible = "renesas,usb2-phy-r9a08g045";
+ reg = <0 0x11e30200 0 0x700>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A08G045_USB_U2H1_HRESETN>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ hsusb: usb@11e20000 {
+ compatible = "renesas,usbhs-r9a08g045",
+ "renesas,rzg2l-usbhs";
+ reg = <0 0x11e20000 0 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A08G045_USB_U2P_EXL_SYSRST>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@12400000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.43.0
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v8 6/7] arm64: dts: renesas: r9a08g045: Add USB support
2025-10-23 13:58 ` [PATCH v8 6/7] arm64: dts: renesas: r9a08g045: Add USB support Claudiu
@ 2025-11-13 15:04 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2025-11-13 15:04 UTC (permalink / raw)
To: Claudiu
Cc: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, magnus.damm,
yoshihiro.shimoda.uh, biju.das.jz, linux-phy, devicetree,
linux-kernel, linux-renesas-soc, Claudiu Beznea, Wolfram Sang
On Thu, 23 Oct 2025 at 17:21, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset,
> host and device support.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks, will queue in renesas-devel for v6.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v8 7/7] arm64: dts: renesas: rzg3s-smarc: Enable USB support
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
` (5 preceding siblings ...)
2025-10-23 13:58 ` [PATCH v8 6/7] arm64: dts: renesas: r9a08g045: Add USB support Claudiu
@ 2025-10-23 13:58 ` Claudiu
2025-10-24 9:15 ` Geert Uytterhoeven
2025-11-13 15:05 ` Geert Uytterhoeven
2025-10-30 12:55 ` [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Philipp Zabel
` (2 subsequent siblings)
9 siblings, 2 replies; 17+ messages in thread
From: Claudiu @ 2025-10-23 13:58 UTC (permalink / raw)
To: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: claudiu.beznea, linux-phy, devicetree, linux-kernel,
linux-renesas-soc, Claudiu Beznea, Wolfram Sang
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Enable USB support (host, device, USB PHYs).
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v8:
- none
Changes in v7:
- none
Changes in v6:
- collected tags
Changes in v5:
- none
Changes in v4:
- none
Changes in v3:
- collected tags
Changes in v2:
- this was patch 15/16 in v1:
- dropped sysc enablement as it is now done in SoC dtsi file
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 57 ++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index 5e044a4d0234..5586dd43c4d5 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -92,6 +92,20 @@ &audio_clk2 {
clock-frequency = <12288000>;
};
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
@@ -132,6 +146,15 @@ power-monitor@44 {
};
};
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
&pinctrl {
audio_clock_pins: audio-clock {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
@@ -207,6 +230,27 @@ ssi3_pins: ssi3 {
<RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
<RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
};
+
+ usb0_pins: usb0 {
+ peri {
+ pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(5, 2, 1)>; /* OVC */
+ };
+
+ otg {
+ pinmux = <RZG2L_PORT_PINMUX(5, 3, 1)>; /* OTG_ID */
+ bias-pull-up;
+ };
+ };
+
+ usb1_pins: usb1 {
+ pinmux = <RZG2L_PORT_PINMUX(5, 4, 5)>, /* OVC */
+ <RZG2L_PORT_PINMUX(6, 0, 1)>; /* VBUS */
+ };
+};
+
+&phyrst {
+ status = "okay";
};
&scif0 {
@@ -242,3 +286,16 @@ &ssi3 {
pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
status = "okay";
};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.43.0
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v8 7/7] arm64: dts: renesas: rzg3s-smarc: Enable USB support
2025-10-23 13:58 ` [PATCH v8 7/7] arm64: dts: renesas: rzg3s-smarc: Enable " Claudiu
@ 2025-10-24 9:15 ` Geert Uytterhoeven
2025-10-24 9:51 ` Claudiu Beznea
2025-11-13 15:05 ` Geert Uytterhoeven
1 sibling, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2025-10-24 9:15 UTC (permalink / raw)
To: Claudiu
Cc: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, magnus.damm,
yoshihiro.shimoda.uh, biju.das.jz, linux-phy, devicetree,
linux-kernel, linux-renesas-soc, Claudiu Beznea, Wolfram Sang
Hi Claudiu,
On Thu, 23 Oct 2025 at 20:41, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Enable USB support (host, device, USB PHYs).
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> &pinctrl {
> audio_clock_pins: audio-clock {
> pins = "AUDIO_CLK1", "AUDIO_CLK2";
> @@ -207,6 +230,27 @@ ssi3_pins: ssi3 {
> <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
> <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
> };
> +
> + usb0_pins: usb0 {
> + peri {
> + pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>, /* VBUS */
> + <RZG2L_PORT_PINMUX(5, 2, 1)>; /* OVC */
> + };
> +
> + otg {
> + pinmux = <RZG2L_PORT_PINMUX(5, 3, 1)>; /* OTG_ID */
> + bias-pull-up;
> + };
> + };
> +
> + usb1_pins: usb1 {
> + pinmux = <RZG2L_PORT_PINMUX(5, 4, 5)>, /* OVC */
> + <RZG2L_PORT_PINMUX(6, 0, 1)>; /* VBUS */
> + };
> +};
> +
> +&phyrst {
> + status = "okay";
> };
This node should be located before pinctrl.
No need to resend just for this.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v8 7/7] arm64: dts: renesas: rzg3s-smarc: Enable USB support
2025-10-24 9:15 ` Geert Uytterhoeven
@ 2025-10-24 9:51 ` Claudiu Beznea
0 siblings, 0 replies; 17+ messages in thread
From: Claudiu Beznea @ 2025-10-24 9:51 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, magnus.damm,
yoshihiro.shimoda.uh, biju.das.jz, linux-phy, devicetree,
linux-kernel, linux-renesas-soc, Claudiu Beznea, Wolfram Sang
Hi, Geert,
On 10/24/25 12:15, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Thu, 23 Oct 2025 at 20:41, Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Enable USB support (host, device, USB PHYs).
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Thanks for your patch!
>
>> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
>
>> &pinctrl {
>> audio_clock_pins: audio-clock {
>> pins = "AUDIO_CLK1", "AUDIO_CLK2";
>> @@ -207,6 +230,27 @@ ssi3_pins: ssi3 {
>> <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
>> <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
>> };
>> +
>> + usb0_pins: usb0 {
>> + peri {
>> + pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>, /* VBUS */
>> + <RZG2L_PORT_PINMUX(5, 2, 1)>; /* OVC */
>> + };
>> +
>> + otg {
>> + pinmux = <RZG2L_PORT_PINMUX(5, 3, 1)>; /* OTG_ID */
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + usb1_pins: usb1 {
>> + pinmux = <RZG2L_PORT_PINMUX(5, 4, 5)>, /* OVC */
>> + <RZG2L_PORT_PINMUX(6, 0, 1)>; /* VBUS */
>> + };
>> +};
>> +
>> +&phyrst {
>> + status = "okay";
>> };
>
> This node should be located before pinctrl.
You're right! I missed it.
> No need to resend just for this.
Thank you!
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v8 7/7] arm64: dts: renesas: rzg3s-smarc: Enable USB support
2025-10-23 13:58 ` [PATCH v8 7/7] arm64: dts: renesas: rzg3s-smarc: Enable " Claudiu
2025-10-24 9:15 ` Geert Uytterhoeven
@ 2025-11-13 15:05 ` Geert Uytterhoeven
1 sibling, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2025-11-13 15:05 UTC (permalink / raw)
To: Claudiu
Cc: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, magnus.damm,
yoshihiro.shimoda.uh, biju.das.jz, linux-phy, devicetree,
linux-kernel, linux-renesas-soc, Claudiu Beznea, Wolfram Sang
On Thu, 23 Oct 2025 at 20:41, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Enable USB support (host, device, USB PHYs).
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks, will queue in renesas-devel for v6.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
` (6 preceding siblings ...)
2025-10-23 13:58 ` [PATCH v8 7/7] arm64: dts: renesas: rzg3s-smarc: Enable " Claudiu
@ 2025-10-30 12:55 ` Philipp Zabel
2025-11-10 15:26 ` Claudiu Beznea
2025-11-20 17:11 ` (subset) " Vinod Koul
9 siblings, 0 replies; 17+ messages in thread
From: Philipp Zabel @ 2025-10-30 12:55 UTC (permalink / raw)
To: Claudiu, vkoul, kishon, robh, krzk+dt, conor+dt, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: linux-phy, devicetree, linux-kernel, linux-renesas-soc,
Claudiu Beznea
On Do, 2025-10-23 at 16:58 +0300, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Hi,
>
> Series adds initial USB support for the Renesas RZ/G3S SoC.
>
> Series is split as follows:
> - patches 1-2/7 - fixes on bindings and driver for USB PHY
> - patches 3-5/7 - updates the rzg2l-usbphy-ctrl driver and documentation
> with support for setting PWRRDY though SYSC
> - patches 6-7/7 - add device tree support
>
> Merge strategy, if any:
> - patches 1-2/7 can go through the PHY tree
> - patches 3-5/7 can go through the reset tree
Patches 3-5 applied to reset/next, thanks!
[3/7] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S
support
https://git.pengutronix.de/cgit/pza/linux/commit/?id=7b129b5de3eb
[4/7] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
https://git.pengutronix.de/cgit/pza/linux/commit/?id=58128aa88867
[5/7] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
https://git.pengutronix.de/cgit/pza/linux/commit/?id=a729c4be5ce9
regards
Philipp
--
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
` (7 preceding siblings ...)
2025-10-30 12:55 ` [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Philipp Zabel
@ 2025-11-10 15:26 ` Claudiu Beznea
2025-11-20 17:11 ` (subset) " Vinod Koul
9 siblings, 0 replies; 17+ messages in thread
From: Claudiu Beznea @ 2025-11-10 15:26 UTC (permalink / raw)
To: vkoul, kishon, robh, krzk+dt, conor+dt, p.zabel, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz
Cc: linux-phy, devicetree, linux-kernel, linux-renesas-soc,
Claudiu Beznea
Hi,
On 10/23/25 16:58, Claudiu wrote:
> Christophe JAILLET (1):
> phy: renesas: rcar-gen3-usb2: Fix an error handling path in
> rcar_gen3_phy_usb2_probe()
>
> Claudiu Beznea (6):
> dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S
Gentle ping on these patches.
Thank you,
Claudiu
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: (subset) [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC
2025-10-23 13:58 [PATCH v8 0/7] Add initial USB support for the Renesas RZ/G3S SoC Claudiu
` (8 preceding siblings ...)
2025-11-10 15:26 ` Claudiu Beznea
@ 2025-11-20 17:11 ` Vinod Koul
9 siblings, 0 replies; 17+ messages in thread
From: Vinod Koul @ 2025-11-20 17:11 UTC (permalink / raw)
To: kishon, robh, krzk+dt, conor+dt, p.zabel, geert+renesas,
magnus.damm, yoshihiro.shimoda.uh, biju.das.jz, Claudiu
Cc: linux-phy, devicetree, linux-kernel, linux-renesas-soc,
Claudiu Beznea
On Thu, 23 Oct 2025 16:58:03 +0300, Claudiu wrote:
> Series adds initial USB support for the Renesas RZ/G3S SoC.
>
> Series is split as follows:
> - patches 1-2/7 - fixes on bindings and driver for USB PHY
> - patches 3-5/7 - updates the rzg2l-usbphy-ctrl driver and documentation
> with support for setting PWRRDY though SYSC
> - patches 6-7/7 - add device tree support
>
> [...]
Applied, thanks!
[1/7] dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S
commit: bc6f8b756c89d831c91a65ef9f3b5ceabdbae441
[2/7] phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe()
commit: 662bb179d3381c7c069e44bb177396bcaee31cc8
Best regards,
--
~Vinod
--
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^ permalink raw reply [flat|nested] 17+ messages in thread