From: neil.armstrong@linaro.org
To: Qiang Yu <quic_qianyu@quicinc.com>,
agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, vkoul@kernel.org, kishon@kernel.org
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, quic_cang@quicinc.com,
quic_mrana@quicinc.com
Subject: Re: [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550
Date: Wed, 24 Jan 2024 09:58:06 +0100 [thread overview]
Message-ID: <e6b8befb-82e8-4803-929c-32e86d1e825a@linaro.org> (raw)
In-Reply-To: <1703742157-69840-1-git-send-email-quic_qianyu@quicinc.com>
On 28/12/2023 06:42, Qiang Yu wrote:
> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware
> Programming Guide.
>
> Can Guo (1):
> phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550
>
> Qiang Yu (1):
> phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550
>
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++++++------
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 +
> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++
> 5 files changed, 21 insertions(+), 6 deletions(-)
>
- On SM8550-HDK:
# lspci
0000:00:00.0 PCI bridge: Qualcomm Device 0113
0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01)
0001:00:00.0 PCI bridge: Qualcomm Device 0113
0001:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation E12 NVMe Controller (rev 01)
# lspci -nvv
0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode])
LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us
LnkSta: Speed 5GT/s, Width x2
0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode])
LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us
LnkSta: Speed 8GT/s, Width x2
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
- On SM8550-QRD:
# lspci
00:00.0 PCI bridge: Qualcomm Device 0113
01:00.0 Network controller: Qualcomm Device 1107 (rev 01)
# lspci -nvv
LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us
LnkSta: Speed 5GT/s, Width x2
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Thanks,
Neil
--
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next prev parent reply other threads:[~2024-01-24 8:58 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-28 5:42 [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 Qiang Yu
2023-12-28 5:42 ` [PATCH 1/2] phy: qcom: qmp-pcie: Update PCIe1 " Qiang Yu
2023-12-28 5:42 ` [PATCH 2/2] phy: qcom: qmp-pcie: Update PCIe0 " Qiang Yu
2024-01-24 8:58 ` neil.armstrong [this message]
2024-01-25 2:59 ` [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe " Qiang Yu
2024-01-25 7:53 ` neil.armstrong
2024-01-25 9:51 ` Konrad Dybcio
2024-01-25 10:13 ` Qiang Yu
2024-01-30 17:39 ` Vinod Koul
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