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Sun, 13 Mar 2022 18:51:16 -0700 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 13 Mar 2022 18:42:18 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 14 Mar 2022 09:42:16 +0800 Received: from mhfsdcap04 (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 14 Mar 2022 09:42:15 +0800 Message-ID: Subject: Re: [PATCH 2/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY From: Jianjun Wang To: Krzysztof Kozlowski , Chunfeng Yun , Kishon Vijay Abraham I , "Vinod Koul" , Rob Herring , Matthias Brugger CC: , , , , , , , , , , Date: Mon, 14 Mar 2022 09:42:15 +0800 In-Reply-To: <0454647b-7aa3-ed70-0b92-1e5c98d0adc0@canonical.com> References: <20220311133527.5914-1-jianjun.wang@mediatek.com> <20220311133527.5914-3-jianjun.wang@mediatek.com> <0454647b-7aa3-ed70-0b92-1e5c98d0adc0@canonical.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220313_185138_011334_A53A05B0 X-CRM114-Status: GOOD ( 22.32 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi Krzysztof, On Fri, 2022-03-11 at 15:28 +0100, Krzysztof Kozlowski wrote: > On 11/03/2022 14:35, Jianjun Wang wrote: > > Add YAML schema documentation for PCIe PHY on MediaTek chipsets. > > > > Signed-off-by: Jianjun Wang > > --- > > .../bindings/phy/mediatek,pcie-phy.yaml | 71 > > +++++++++++++++++++ > > 1 file changed, 71 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie- > > phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie- > > phy.yaml > > new file mode 100644 > > index 000000000000..da15b4bf3117 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > @@ -0,0 +1,71 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek PCIe PHY Device Tree Binding > > Title is for hardware, so s/Device Tree Binding// > > > + > > +maintainers: > > + - Jianjun Wang > > + > > +description: | > > + The PCIe PHY supports physical layer functionality for PCIe Gen3 > > port. > > + > > +properties: > > + compatible: > > + const: mediatek,pcie-phy > > Is it going to be exactly one pcie-phy for all Mediatek chipsets for > next years? Are you sure about that? It sounds highly unlikely.... We have only one pcie-phy for now, but if this is not recommended, I will replace it with a specific name in the next version, thanks for your review. Thanks. > > > + > > + reg: > > + maxItems: 1 > > + > > + reg-names: > > + items: > > + - const: sif > > + > > + "#phy-cells": > > + const: 0 > > + > > + nvmem-cells: > > + maxItems: 7 > > + description: > > + Phandles to nvmem cell that contains the efuse data, if > > unspecified, > > + default value is used. > > + > > + nvmem-cell-names: > > + items: > > + - const: glb_intr > > + - const: tx_ln0_pmos > > + - const: tx_ln0_nmos > > + - const: rx_ln0 > > + - const: tx_ln1_pmos > > + - const: tx_ln1_nmos > > + - const: rx_ln1 > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - "#phy-cells" > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + pciephy: phy@11e80000 { > > + compatible = "mediatek,pcie-phy"; > > + #phy-cells = <0>; > > + reg = <0x11e80000 0x10000>; > > + reg-names = "sif"; > > + nvmem-cells = <&pciephy_glb_intr>, > > + <&pciephy_tx_ln0_pmos>, > > + <&pciephy_tx_ln0_nmos>, > > + <&pciephy_rx_ln0>, > > + <&pciephy_tx_ln1_pmos>, > > + <&pciephy_tx_ln1_nmos>, > > + <&pciephy_rx_ln1>; > > + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", > > + "tx_ln0_nmos", "rx_ln0", > > + "tx_ln1_pmos", "tx_ln1_nmos", > > + "rx_ln1"; > > + }; > > > Best regards, > Krzysztof -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy