* [PATCH] phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence
@ 2025-06-25 7:00 Kathiravan Thirumoorthy
2025-06-25 13:58 ` Konrad Dybcio
0 siblings, 1 reply; 3+ messages in thread
From: Kathiravan Thirumoorthy @ 2025-06-25 7:00 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Bjorn Andersson,
Varadarajan Narayanan
Cc: linux-arm-msm, linux-phy, linux-kernel, stable,
Kathiravan Thirumoorthy
The current configuration used for the IPQ5332 M31 USB PHY fails the
Near End High Speed Signal Quality compliance test. To resolve this,
update the initialization sequence as specified in the Hardware Design
Document.
Fixes: 08e49af50701 ("phy: qcom: Introduce M31 USB PHY driver")
Cc: stable@kernel.org
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-m31.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
index 7caeea1b109e922c0cd12e985bc8868d5bce8b4f..1a8a0f1262cd95bc00dfbf7397a1c48d88d52327 100644
--- a/drivers/phy/qualcomm/phy-qcom-m31.c
+++ b/drivers/phy/qualcomm/phy-qcom-m31.c
@@ -58,12 +58,14 @@
#define USB2_0_TX_ENABLE BIT(2)
#define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
- #define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
+ #define HSTX_SLEW_RATE_400PS GENMASK(2, 0)
#define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
#define ODT_VALUE_38_02_OHM GENMASK(7, 6)
+#define USB2PHY_USB_PHY_M31_XCFGI_9 0xDC
+#define HSTX_CURRENT_17_1MA_385MV BIT(1)
+
#define USB2PHY_USB_PHY_M31_XCFGI_5 0xcc
- #define ODT_VALUE_45_02_OHM BIT(2)
#define HSTX_PRE_EMPHASIS_LEVEL_0_55MA BIT(0)
#define USB2PHY_USB_PHY_M31_XCFGI_11 0xe4
@@ -164,7 +166,7 @@ static struct m31_phy_regs m31_ipq5332_regs[] = {
},
{
USB2PHY_USB_PHY_M31_XCFGI_4,
- HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA | ODT_VALUE_38_02_OHM,
+ HSTX_SLEW_RATE_400PS | PLL_CHARGING_PUMP_CURRENT_35UA | ODT_VALUE_38_02_OHM,
0
},
{
@@ -174,9 +176,13 @@ static struct m31_phy_regs m31_ipq5332_regs[] = {
},
{
USB2PHY_USB_PHY_M31_XCFGI_5,
- ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA,
+ HSTX_PRE_EMPHASIS_LEVEL_0_55MA,
4
},
+ {
+ USB2PHY_USB_PHY_M31_XCFGI_9,
+ HSTX_CURRENT_17_1MA_385MV,
+ },
{
USB_PHY_UTMI_CTRL5,
0x0,
---
base-commit: 2ae2aaafb21454f4781c30734959cf223ab486ef
change-id: 20250625-ipq5332_hsphy_complaince-c45be2e7224a
Best regards,
--
Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence
2025-06-25 7:00 [PATCH] phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence Kathiravan Thirumoorthy
@ 2025-06-25 13:58 ` Konrad Dybcio
2025-06-26 4:13 ` Kathiravan Thirumoorthy
0 siblings, 1 reply; 3+ messages in thread
From: Konrad Dybcio @ 2025-06-25 13:58 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Vinod Koul, Kishon Vijay Abraham I,
Bjorn Andersson, Varadarajan Narayanan
Cc: linux-arm-msm, linux-phy, linux-kernel, stable
On 6/25/25 9:00 AM, Kathiravan Thirumoorthy wrote:
> The current configuration used for the IPQ5332 M31 USB PHY fails the
> Near End High Speed Signal Quality compliance test. To resolve this,
> update the initialization sequence as specified in the Hardware Design
> Document.
>
> Fixes: 08e49af50701 ("phy: qcom: Introduce M31 USB PHY driver")
> Cc: stable@kernel.org
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-m31.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
> index 7caeea1b109e922c0cd12e985bc8868d5bce8b4f..1a8a0f1262cd95bc00dfbf7397a1c48d88d52327 100644
> --- a/drivers/phy/qualcomm/phy-qcom-m31.c
> +++ b/drivers/phy/qualcomm/phy-qcom-m31.c
> @@ -58,12 +58,14 @@
> #define USB2_0_TX_ENABLE BIT(2)
>
> #define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
> - #define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
> + #define HSTX_SLEW_RATE_400PS GENMASK(2, 0)
> #define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
> #define ODT_VALUE_38_02_OHM GENMASK(7, 6)
>
> +#define USB2PHY_USB_PHY_M31_XCFGI_9 0xDC
lowercase hex, please
also, please add it below XCFGI_5, so that it's sorted
both by name and by address
FWIW I can't find anything that would back up these changes, but
I trust what you're saying is true
Konrad
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence
2025-06-25 13:58 ` Konrad Dybcio
@ 2025-06-26 4:13 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 3+ messages in thread
From: Kathiravan Thirumoorthy @ 2025-06-26 4:13 UTC (permalink / raw)
To: Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
Bjorn Andersson, Varadarajan Narayanan
Cc: linux-arm-msm, linux-phy, linux-kernel, stable
On 6/25/2025 7:28 PM, Konrad Dybcio wrote:
> On 6/25/25 9:00 AM, Kathiravan Thirumoorthy wrote:
>> The current configuration used for the IPQ5332 M31 USB PHY fails the
>> Near End High Speed Signal Quality compliance test. To resolve this,
>> update the initialization sequence as specified in the Hardware Design
>> Document.
>>
>> Fixes: 08e49af50701 ("phy: qcom: Introduce M31 USB PHY driver")
>> Cc: stable@kernel.org
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>> drivers/phy/qualcomm/phy-qcom-m31.c | 14 ++++++++++----
>> 1 file changed, 10 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
>> index 7caeea1b109e922c0cd12e985bc8868d5bce8b4f..1a8a0f1262cd95bc00dfbf7397a1c48d88d52327 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-m31.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-m31.c
>> @@ -58,12 +58,14 @@
>> #define USB2_0_TX_ENABLE BIT(2)
>>
>> #define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
>> - #define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
>> + #define HSTX_SLEW_RATE_400PS GENMASK(2, 0)
>> #define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
>> #define ODT_VALUE_38_02_OHM GENMASK(7, 6)
>>
>> +#define USB2PHY_USB_PHY_M31_XCFGI_9 0xDC
> lowercase hex, please
>
> also, please add it below XCFGI_5, so that it's sorted
> both by name and by address
Ack. Will address this in V2.
>
> FWIW I can't find anything that would back up these changes, but
> I trust what you're saying is true
Thank You!. These changes are tested and confirmed by the relevant
folks. I will try to find the doc and share it offline for reference.
>
> Konrad
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2025-06-25 7:00 [PATCH] phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence Kathiravan Thirumoorthy
2025-06-25 13:58 ` Konrad Dybcio
2025-06-26 4:13 ` Kathiravan Thirumoorthy
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