Re: [PATCH v8 5/5] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100

Qiang Yu
2024-11-11T03:51:27Z

On 11/5/2024 1:28 PM, Qiang Yu wrote:
>
> On 11/4/2024 10:35 PM, Johan Hovold wrote:
>> On Thu, Oct 31, 2024 at 08:09:02PM -0700, Qiang Yu wrote:
>>> Describe PCIe3 controller and PHY. Also add required system
>>> resources like
>>> regulators, clocks, interrupts and registers configuration for PCIe3.
>>>
>>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
>>> +        pcie3: pcie@1bd0000 {
>>> +            device_type = "pci";
>>> +            compatible = "qcom,pcie-x1e80100";
>>> +            reg = <0x0 0x01bd0000 0x0 0x3000>,
>>> +                  <0x0 0x78000000 0x0 0xf1d>,
>>> +                  <0x0 0x78000f40 0x0 0xa8>,
>>> +                  <0x0 0x78001000 0x0 0x1000>,
>>> +                  <0x0 0x78100000 0x0 0x100000>,
>>> +                  <0x0 0x01bd3000 0x0 0x1000>;
>>> +            reg-names = "parf",
>>> +                    "dbi",
>>> +                    "elbi",
>>> +                    "atu",
>>> +                    "config",
>>> +                    "mhi";
>>> +            #address-cells = <3>;
>>> +            #size-cells = <2>;
>>> +            ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0
>>> 0x100000>,
>>> +                 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0
>>> 0x3d00000>,
>> Can you double check the size here so that it is indeed correct and not
>> just copied from the other nodes which initially got it wrong:
>>
>>     https://lore.kernel.org/lkml/20240710-topic-barman-v1-1-5f63fca8d0fc@linaro.org/
BTW, regions of PCIe6a, PCIe4, PCIe5 are 64MB, 32MB, 32MB, respectively.
Why range size is set to 0x1d00000 for PCIe6a, any issue is reported on
PCIe6a?

Thanks,
Qiang Yu
> From memory maps, region of PCIe3 is 64MB, the size here is correct.
>
> Thanks,
> Qiang Yu
>>
>>> +                 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0
>>> 0x40000000>;
>>> +            bus-range = <0x00 0xff>;
>>> +            clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
>>> +                 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
>>> +                 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
>>> +                 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
>>> +                 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
>>> +                 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
>>> +                 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
>>> +            clock-names = "aux",
>>> +                      "cfg",
>>> +                      "bus_master",
>>> +                      "bus_slave",
>>> +                      "slave_q2a",
>>> +                      "noc_aggr",
>>> +                      "cnoc_sf_axi";
>>> +
>>> +            assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
>>> +            assigned-clock-rates = <19200000>;
>>> +
>>> +            interconnects = <&pcie_south_anoc MASTER_PCIE_3
>>> QCOM_ICC_TAG_ALWAYS
>> This should be &pcie_north_anoc
>>
>>> +                     &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>> +                    <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>> +                     &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
>>> +            interconnect-names = "pcie-mem",
>>> +                         "cpu-pcie";
>> With the above addressed, feel free to keep my Reviewed-by tag.
>>
>> Johan